Copper Indium Gallium DiSelenide absorber layers are fabricated using a two stage manufacturing friendly process. The first step involves the sequential deposition of Copper and Gallium and co-deposition of indium and selenium at 275oC. This is followed by the second stage where the substrate is annealed in the presence of Selenium and a thin layer of copper is deposited to neutralize the excess Indium and Gallium on the surface to form the CIGS absorber layer. The top copper thickness as well as the time of deposition was varied to study the effect of Copper on the performance of the cells. Another recipe was developed for the precursor formation, where Gallium was co-evaporated with Indium and Selenium. A large bandgap shift was seen with this recipe and the open circuit voltage was increased. The performance of CIGS/CdS/ZnO solar cells thus fabricated was characterized using techniques like I-V, C-V, Spectral Response and EDS/SEM. Cells with open circuit voltages of 420-450 mV, short circuit currents of 33-38 mA/cm², fill factors of 58-62% and efficiencies of 9-11% were routinely fabricated.