In this study, it was nanoimprint focused on the anti-adhesion technique between the grating structure silicon molds below 200nm half-pitch and polymer materials (H-PDMS). The nano-groove structure molds with different depths and widths were made by FIB. During the process of molding by soft-lithography, an anti-adhesion layer needed being plated between the silicon and PDMS mold, which was in order to get completely formed H-PDMS soft mold and prevent defective mold caused by the adhesion problem on the surface. There were three kinds of method of plating anti-adhesion layer which were the liquid immersion, vapor deposition, and fluorine doped DLC film. The PFOTCS was used as mold releasing agent in the methods of liquid immersion and vapor deposition, and the contact angle was measured to realize the ability of anti-adhesion. In the method of fluorine doped DLC film, in addition to measuring the anti-adhesion ability for each sample through contact angle with water, the AFM was also applied to measure the degree of adhesion on the surface for each film. And the contact angles with water between each film were also compared. The methods of plating anti-adhesion film with lower degree of adhesion on the surface could be acquired and discussed by means of the above-mentioned ways to fabricate the molds with good formability

The packing density of microelectronic devices has increased exponentially over the past four decades. Continuous enhancements in device performance and functionality have been achieved by the introduction of new materials and fabrication techniques. This thesis summarizes the thin film materials and metallization processes by chemical vapor deposition (CVD) developed during my graduate study with Professor Gordon at Harvard University. These materials and processes have the potential to build future generations of microelectronic devices with higher speeds and longer lifetimes. Manganese Silicate Diffusion Barrier: Highly conformal, amorphous and insulating manganese silicate \((MnSi_xO_y)\) layers are formed along the walls of trenches in interconnects by CVD using a manganese amidinate precursor vapor that reacts with the surfaces of the insulators. These \((MnSi_xO_y)\) layers are excellent barriers to diffusion of copper, oxygen and water. Manganese Capping Layer: A selective CVD manganese capping process strengthens the interface between copper and dielectric insulators to improve the electromigration reliability of the interconnects. High selectivity is achieved by deactivating the insulator surfaces using vapors containing reactive methylsilyl groups. Manganese at the Cu/insulator interface greatly increases the strength of adhesion between the copper and the insulator. Bottom-up Filling of Copper and Alloy in Narrow Features: Narrow trenches, with widths narrow than 30 nm and aspect ratios up to 9:1, can be filled with copper or copper-manganese alloy in a bottom-up fashion using a surfactant-catalyzed CVD process. A conformal manganese nitride \((Mn_4N)\) layer serves as a diffusion barrier and adhesion layer. Iodine atoms chemisorb on the \(Mn_4N\) layer and are then released to act as a catalytic surfactant on the surface of the growing copper layer to achieve void-free, bottom-up filling. Upon post-annealing, manganese in the alloy diffuses out from the copper and forms a self-aligned barrier in the surface of the insulator. Conformal Seed Layers for Plating Through-Silicon Vias: Through-silicon vias (TSV) will speed up interconnections between chips. Conformal, smooth and continuous seed layers in TSV holes with aspect ratios greater than 25:1 can be prepared using vapor deposition techniques. \(Mn_4N\) is deposited conformally on the silica surface by CVD to provide strong adhesion at Cu/insulator interface. Conformal copper or Cu-Mn alloy seed layers are then deposited by an iodine-catalyzed direct-liquid-injection (DLI) CVD process. / Chemistry and Chemical Biology

Master of Science / Electrical and Computer Engineering / William B. Kuhn / At RF frequencies and beyond, metallic circuit interconnects no longer behave as lumped-element wires; instead they exhibit distributed-element behavior and are classified as transmission lines. Power losses on transmission lines are of great concern to RF and microwave engineers and great care is taken to minimize power losses while still maintaining application-based robustness. The combination of low-temperature co-fire ceramics (LTCCs) and thin-film transmission line fabrication allows application-specific robustness and excellent microwave and millimeter wave performance to be achieved. LTCC technology provides a low-loss microwave substrate and allows for thin-film metal and insulator depositions to form precision transmission-line geometries and surface-applique capacitors. In the field of thin-film metals however, concern over excess power losses at high frequencies has arisen due to the necessity of a high-resistance metallic adhesion layer which is required for the mechanical adhesion of the transmission lines to the LTCC substrate. This is especially worrisome in a microstrip configuration where the current density is concentrated at the substrate-metal interface; exactly where the high-loss metal is situated. This thesis shows that if the high-resistance adhesion layer is limited to a thickness which is a fraction of its skin depth, with more conductive metals layered above, then those excessive resistive losses can be avoided. Issues with decreasing the total thickness of the thin-film layered metals are also investigated to achieve better interconnect line-and-space resolution, which is required for electronics operating at millimeter-wave bandwidths. Several test cases show that thinning of the metal layers has minimal impact on electrical performance. However, poor signal integrity is observed when the finished thickness of the metal stack up is reduced below 1μm. Further testing reveals that surface roughness leads to manufacturing issues when trying to produce thin-films with thicknesses in the sub-micron range. Finally, a novel bypass and coupling capacitor topology is proposed and investigated. The capacitors are simple thin-film metal-insulator-metal constructions designed for use in a flip-chip mounting environment. Testing shows the capacitors exhibit a very low impedance through 20 GHz making them an ideal board-level bypass solution. This technology has the potential to replace all but the large bulk charge storage capacitors in electronic designs, increasing performance and mechanical robustness, while simultaneously decreasing bill of material cost and PCB assembly times.

abstract: In this dissertation, remote plasma interactions with the surfaces of low-k interlayer dielectric (ILD), Cu and Cu adhesion layers are investigated. The first part of the study focuses on the simultaneous plasma treatment of ILD and chemical mechanical polishing (CMP) Cu surfaces using N2/H2 plasma processes. H atoms and radicals in the plasma react with the carbon groups leading to carbon removal for the ILD films. Results indicate that an N2 plasma forms an amide-like layer on the surface which apparently leads to reduced carbon abstraction from an H2 plasma process. In addition, FTIR spectra indicate the formation of hydroxyl (Si-OH) groups following the plasma exposure. Increased temperature (380 °C) processing leads to a reduction of the hydroxyl group formation compared to ambient temperature processes, resulting in reduced changes of the dielectric constant. For CMP Cu surfaces, the carbonate contamination was removed by an H2 plasma process at elevated temperature while the C-C and C-H contamination was removed by an N2 plasma process at elevated temperature. The second part of this study examined oxide stability and cleaning of Ru surfaces as well as consequent Cu film thermal stability with the Ru layers. The ~2 monolayer native Ru oxide was reduced after H-plasma processing. The thermal stability or islanding of the Cu film on the Ru substrate was characterized by in-situ XPS. After plasma cleaning of the Ru adhesion layer, the deposited Cu exhibited full coverage. In contrast, for Cu deposition on the Ru native oxide substrate, Cu islanding was detected and was described in terms of grain boundary grooving and surface and interface energies. The thermal stability of 7 nm Ti, Pt and Ru ii interfacial adhesion layers between a Cu film (10 nm) and a Ta barrier layer (4 nm) have been investigated in the third part. The barrier properties and interfacial stability have been evaluated by Rutherford backscattering spectrometry (RBS). Atomic force microscopy (AFM) was used to measure the surfaces before and after annealing, and all the surfaces are relatively smooth excluding islanding or de-wetting phenomena as a cause of the instability. The RBS showed no discernible diffusion across the adhesion layer/Ta and Ta/Si interfaces which provides a stable underlying layer. For a Ti interfacial layer RBS indicates that during 400 °C annealing Ti interdiffuses through the Cu film and accumulates at the surface. For the Pt/Cu system Pt interdiffuion is detected which is less evident than Ti. Among the three adhesion layer candidates, Ru shows negligible diffusion into the Cu film indicating thermal stability at 400 °C. / Dissertation/Thesis / Ph.D. Physics 2012

The integration of copper (Cu) and dielectric materials has been outlined in the International Technology Roadmap for Semiconductors (ITRS) as a critical goal for future microelectronic devices. A necessity toward achieving this goal is the development of diffusion barriers that resolve the Cu and dielectric incompatibility. The focus of this research examines the potential use of tungsten nitride as a diffusion barrier by characterizing the interfacial properties with Cu and evaluating its process capability for industrial use. Tungsten nitride (β-W2N) development has been carried out using a plasma enhanced chemical vapor deposition (PECVD) technique that utilizes tungsten hexafluoride (WF6), nitrogen (N2), hydrogen (H2), and argon (Ar). Two design of experiments (DOE) were performed to optimize the process with respect to film stoichiometry, resistivity and uniformity across a 200 mm diameter Si wafer. Auger depth profiling showed a 2:1 W:N ratio. X-ray diffraction (XRD) showed a broad peak centered on the β-W2N phase. Film resistivity was 270 mohm-cm and film uniformity < 3 %. The step coverage (film thickness variance) across a structured etched dielectric (SiO2, 0.35 mm, 3:1 aspect ratio) was > 44 %. Secondary ion mass spectroscopy (SIMS) measurements showed good barrier performance for W2N between Cu and SiO2 with no intermixing of the Cu and silicon when annealed to 390o C for 3 hours. Cu nucleation behavior and thermal stability on clean and nitrided tungsten foil (WxN = δ-WN and β-W2N phases) have been characterized by Auger electron spectroscopy (AES) and thermal desorption spectroscopy (TDS) under controlled ultra high vacuum (UHV) conditions. At room temperature, the Auger intensity ratio vs. time plots demonstrates layer by layer Cu growth for the clean tungsten (W) surface and three-dimensional nucleation for the nitride overlayer. Auger intensity ratio vs. temperature measurements for the Cu/W system indicates a stable interface up to 1000 K. For the Cu /WxN/W system, initial Cu diffusion into the nitride overlayer is observed at 550 K.