abstract: In this dissertation, remote plasma interactions with the surfaces of low-k interlayer dielectric (ILD), Cu and Cu adhesion layers are investigated. The first part of the study focuses on the simultaneous plasma treatment of ILD and chemical mechanical polishing (CMP) Cu surfaces using N2/H2 plasma processes. H atoms and radicals in the plasma react with the carbon groups leading to carbon removal for the ILD films. Results indicate that an N2 plasma forms an amide-like layer on the surface which apparently leads to reduced carbon abstraction from an H2 plasma process. In addition, FTIR spectra indicate the formation of hydroxyl (Si-OH) groups following the plasma exposure. Increased temperature (380 °C) processing leads to a reduction of the hydroxyl group formation compared to ambient temperature processes, resulting in reduced changes of the dielectric constant. For CMP Cu surfaces, the carbonate contamination was removed by an H2 plasma process at elevated temperature while the C-C and C-H contamination was removed by an N2 plasma process at elevated temperature. The second part of this study examined oxide stability and cleaning of Ru surfaces as well as consequent Cu film thermal stability with the Ru layers. The ~2 monolayer native Ru oxide was reduced after H-plasma processing. The thermal stability or islanding of the Cu film on the Ru substrate was characterized by in-situ XPS. After plasma cleaning of the Ru adhesion layer, the deposited Cu exhibited full coverage. In contrast, for Cu deposition on the Ru native oxide substrate, Cu islanding was detected and was described in terms of grain boundary grooving and surface and interface energies. The thermal stability of 7 nm Ti, Pt and Ru ii interfacial adhesion layers between a Cu film (10 nm) and a Ta barrier layer (4 nm) have been investigated in the third part. The barrier properties and interfacial stability have been evaluated by Rutherford backscattering spectrometry (RBS). Atomic force microscopy (AFM) was used to measure the surfaces before and after annealing, and all the surfaces are relatively smooth excluding islanding or de-wetting phenomena as a cause of the instability. The RBS showed no discernible diffusion across the adhesion layer/Ta and Ta/Si interfaces which provides a stable underlying layer. For a Ti interfacial layer RBS indicates that during 400 °C annealing Ti interdiffuses through the Cu film and accumulates at the surface. For the Pt/Cu system Pt interdiffuion is detected which is less evident than Ti. Among the three adhesion layer candidates, Ru shows negligible diffusion into the Cu film indicating thermal stability at 400 °C. / Dissertation/Thesis / Ph.D. Physics 2012

Nanoporous low-k dielectrics are used for integrated circuit interconnects to reduce the propagation delays, and cross talk noise between metal wires as an alternative material for SiO2. These materials, typically organosilicate glass (OSG) films, are exposed to oxygen plasmas during photoresist stripping and related processes which substantially damage the film by abstracting carbon, incorporating O and OH, eventually leading to significantly increased k values. Systematic studies have been performed to understand the oxygen plasma-induced damage mechanisms on different low-k OSG films of various porosity and pore interconnectedness. Fourier transform infrared spectroscopy, x-ray photoelectron spectroscopy and atomic force microscopy are used to understand the damage kinetics of O radicals, ultraviolet photons and charged species, and possible ways to control the carbon loss from the film. FTIR results demonstrate that O radical present in the plasma is primarily responsible for carbon abstraction and this is governed by diffusion mechanism involving interconnected film nanopores. The loss of carbon from the film can be controlled by closing the pore interconnections, He plasma pretreatment is an effective way to control the damage at longer exposure by closing the connections between the pores.

Low-k dielectrics with porosity are being introduced to reduce the RC delay of Cu/low-k interconnect. However, during the O2 plasma ashing process, the porous low-k dielectrics tend to degrade due to methyl depletion, moisture uptake, and densification, increasing the dielectric constant and leakage current. This dissertation presents a study of the mechanisms of plasma damage and dielectric recovery. The kinetics of plasma interaction with low-k dielectrics was investigated both experimentally and theoretically. By using a gap structure, the roles of ion, photon, and radical in producing damage on low-k dielectrics were differentiated. Oxidative plasma induced damage was proportional to the oxygen radical density, enhanced by VUV photon, and increased with substrate temperature. Ion bombardment induced surface densification, blocking radical diffusion. Two analytical models were derived to quantify the plasma damage. Based on the radical diffusion, reaction, and recombination inside porous low-k dielectrics, a plasma altered layer model was derived to interpret the chemical effect in the low ion energy region. It predicted that oxidative plasma induced damage can be reduced by decreasing pore radius, substrate temperature, and oxygen radical density and increasing carbon concentration and surface recombination rate inside low-k dielectrics. The model validity was verified by experiments and Monte-Carlo simulations. This model was also extended to the patterned low-k structure. Based on the ion collision cascade process, a sputtering yield model was introduced to interpret the physical effect in the high ion energy region. The model validity was verified by checking the ion angular and energy dependences of sputtering yield using O2/He/Ar plasma, low-k dielectrics with different k values, and a Faraday cage. Low-k dielectrics and plasma process were optimized to reduce plasma damage, including increasing carbon concentration in low-k dielectrics, switching plasma generator from ICP to RIE, increasing hard mask thickness, replacing O2 by CO2 plasma, increasing CO addition in CO/O2 plasma, and increasing N2 addition in CO2/N2 plasma. By combining analytical techniques with the Kramers-Kronig dispersion relation and quantum chemistry calculation, the origin of dielectric loss was ascribed to the physisorbed water molecules. Post-ash CH4 plasma treatment, vapor silylation process, and UV radiation were developed to repair plasma damage. / text

Plasma induced damage of ultra low-k (ULK) dielectrics is a common phenomenon in BEOL interconnects. The damage leads to an increase in k-value, which raises the RC delay, leading to increased power consumption and cross talk noise. Therefore, diverse repair and post etch treatments (PET) have been proposed to restore or reduce the ULK damage. However, current repair processes are usually based on non-plasma silylation, which suffers from limited chemistry diffusion into the ULK. Moreover, the conventional PET based on anisotropic plasma results in bottom vs. sidewall inhomogeneities of the structures (e.g. via and trench). To reduce these drawbacks, an organosilane downstream -plasma (DSP) was applied. This new application resulted in an increased resistance to ULK removal by fluorinated wet clean chemistries, preserving the ULK hydrophobicity, keeping its carbon content relatively high. The effective RC measured on 28 nm node patterned wafers treated with a DSP PET remains nevertheless comparable to the process of record (POR).

Since its inception as the Tungsten Workshop in 1984, AMC has served as the leading conference for the interconnect and contact metallization communities, and has remained at the leading edge of the development of tungsten, aluminum, and copper/low-K interconnects. As the semiconductor industry evolves, exciting new challenges in metallization are emerging, particularly in the areas of contacts to advanced devices, local interconnect solutions for highly-scaled devices, advanced memory device metallization, and 3D/packaging technology. While the conference content has evolved, the unique workshop environment of AMC fosters open discussion to create opportunities for cross-pollination between academia and industry. Submissions are covering materials, process, integration and reliability challenges spanning a wide range of topics in metallization for interconnect/contact applications, especially in the areas of: - Contacts to advanced devices (FinFET, Nanowire, III/V, and 2D materials) - Highly-scaled local and global interconnects - Beyond Cu interconnect - Novel metallization schemes and advanced dielectrics - Interconnect and device reliability - Advanced memory (NAND/DRAM, 3D NAND, STT and RRAM) - 3D and packaging (monolithic 3D, TSV, EMI) - Novel and emerging interconnects Executive Committee: Sang Hoon Ahn (Samsung Electronics Co., Ltd.) Paul R. Besser (Lam Research) Robert S. Blewer (Blewer Scientific Consultants, LLC) Daniel Edelstein (IBM) John Ekerdt (The University of Texas at Austin) Greg Herdt (Micron) Chris Hobbs (Sematech) Francesca Iacopi (Griffith University) Chia-Hong Jan (Intel Corporation) Rajiv Joshi (IBM) Heinrich Koerner (Infineon Technologies) Mehul Naik (Applied Materials Inc.) Fabrice Nemouchi (CEA LETI MINATEC) Takayuki Ohba (Tokyo Institute of Technology) Noel Russell (TEL Technology Center, America) Stefan E. Schulz (Chemnitz University of Technology) Yosi Shacham-Diamand (Tel-Aviv University) Roey Shaviv (Applied Materials Inc.) Zsolt Tokei (IMEC)

Since its inception as the Tungsten Workshop in 1984, AMC has served as the leading conference for the interconnect and contact metallization communities, and has remained at the leading edge of the development of tungsten, aluminum, and copper/low-K interconnects. As the semiconductor industry evolves, exciting new challenges in metallization are emerging, particularly in the areas of contacts to advanced devices, local interconnect solutions for highly-scaled devices, advanced memory device metallization, and 3D/packaging technology. While the conference content has evolved, the unique workshop environment of AMC fosters open discussion to create opportunities for cross-pollination between academia and industry. Submissions are covering materials, process, integration and reliability challenges spanning a wide range of topics in metallization for interconnect/contact applications, especially in the areas of: - Contacts to advanced devices (FinFET, Nanowire, III/V, and 2D materials) - Highly-scaled local and global interconnects - Beyond Cu interconnect - Novel metallization schemes and advanced dielectrics - Interconnect and device reliability - Advanced memory (NAND/DRAM, 3D NAND, STT and RRAM) - 3D and packaging (monolithic 3D, TSV, EMI) - Novel and emerging interconnects Executive Committee: Sang Hoon Ahn (Samsung Electronics Co., Ltd.) Paul R. Besser (Lam Research) Robert S. Blewer (Blewer Scientific Consultants, LLC) Daniel Edelstein (IBM) John Ekerdt (The University of Texas at Austin) Greg Herdt (Micron) Chris Hobbs (Sematech) Francesca Iacopi (Griffith University) Chia-Hong Jan (Intel Corporation) Rajiv Joshi (IBM) Heinrich Koerner (Infineon Technologies) Mehul Naik (Applied Materials Inc.) Fabrice Nemouchi (CEA LETI MINATEC) Takayuki Ohba (Tokyo Institute of Technology) Noel Russell (TEL Technology Center, America) Stefan E. Schulz (Chemnitz University of Technology) Yosi Shacham-Diamand (Tel-Aviv University) Roey Shaviv (Applied Materials Inc.) Zsolt Tokei (IMEC)

The impact of physical design characteristics on backend dielectric reliability was modeled. The impact of different interconnect geometries on backend low-k time dependent dielectric breakdown was reported and modeled. Physical design parameters that are crucial to backend dielectric reliability were identified. A methodology was proposed for determining chip reliability but combining the insights gathered by modeling the impact of physical design on backend dielectric breakdown. A methodology to model variation in device parameters and characteristics was proposed. New methods of electrical and physical parameter extraction were proposed. Models that consider systematic and random source of variation in electrical and physical parameters of CMOS devices were proposed, to aid in circuit design and timing analysis.