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Yau Chi-kit. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2002. / Includes bibliographical references (leaves 149-151). / Abstracts in English and Chinese. / Abstract / Acknowledgements / Table of Contents / Chapter Chapter 1 --- Introduction --- p.1 / Chapter Chapter 2 --- Background Theory --- p.5 / Chapter 2.1 --- Power Dividers and Couplers --- p.5 / Chapter 2.1.1 --- 3dB Wilkinson Power Divider --- p.5 / Chapter 2.1.2 --- Branch Line Coupler --- p.9 / Chapter 2.2 --- Balanced Amplifier --- p.11 / Chapter 2.2.1 --- Working Mechanism of Balanced Amplifier --- p.11 / Chapter 2.2.2 --- Effects of Coupler's Phase Imbalance and Gain Mismatch --- p.15 / Chapter 2.3 --- Low Temperature Co-fired Ceramic (LTCC) Technology --- p.21 / Chapter 2.3.1 --- Overview of LTCC Technology --- p.21 / Chapter 2.3.2 --- LTCC Material Properties and Performance --- p.23 / Chapter 2.3.3 --- Advantages and Disadvantages of LTCC Technology --- p.24 / Chapter Chapter 3 --- LTCC Basic Components Characterization --- p.27 / Chapter 3.1 --- Embedded Capacitors --- p.28 / Chapter 3.1.1 --- Vertical Structure for Embedded Capacitors --- p.28 / Chapter 3.1.2 --- Shunt Capacitor --- p.29 / Chapter 3.1.3 --- Series Capacitor --- p.45 / Chapter 3.2 --- Embedded Inductors --- p.54 / Chapter 3.2.1 --- Shunt Inductor --- p.54 / Chapter 3.2.2 --- Series Inductor --- p.61 / Chapter Chapter 4 --- Design Methodology for LTCC Integrated Passive Devices (IPD) --- p.69 / Chapter 4.1 --- LTCC Circuit Design Roadmap --- p.70 / Chapter 4.2 --- Design of a 1.88GHz Lumped Element 3dB Branch Line Coupler --- p.73 / Chapter 4.2.1 --- Vertical Structure --- p.73 / Chapter 4.2.2 --- Design Specifications --- p.74 / Chapter 4.2.3 --- Schematic Design --- p.74 / Chapter 4.2.4 --- Design Library --- p.79 / Chapter 4.2.5 --- Commercial EM Simulator --- p.83 / Chapter 4.2.6 --- Layout and Optimization Designs --- p.89 / Chapter 4.3 --- Design of a 1.88GHz Lumped Element 3dB Wilkinson's Power Divider with 90° phase difference between two outputs --- p.96 / Chapter 4.4 --- 3-port Measurement Technique --- p.106 / Chapter Chapter 5 --- Noise Analysis and Noise Parameters Measurement --- p.110 / Chapter 5.1 --- Noise Figure of an Amplifier --- p.110 / Chapter 5.2 --- Noise Correlation Matrices --- p.114 / Chapter 5.2.1 --- Definition --- p.114 / Chapter 5.2.2 --- Transformation of Representation --- p.116 / Chapter 5.2.3 --- Connection of Correlation Matrices --- p.117 / Chapter 5.3 --- Noise Characterization --- p.118 / Chapter 5.3.1 --- Conventional Measurement Technique --- p.118 / Chapter 5.3.2 --- Determination of Noise Parameters Using Four Nonsingular Measurements --- p.119 / Chapter 5.3.3 --- A De-embedding Technique for Extracting Noise Parameters --- p.121 / Chapter Chapter 6 --- Design of a 1.88GHz LTCC Balanced LNA --- p.126 / Chapter 6.1 --- Design Specifications --- p.126 / Chapter 6.2 --- Design of LTCC D.C. Biasing Circuit --- p.128 / Chapter 6.3 --- Stability Consideration --- p.129 / Chapter 6.4 --- Matching Networks Design --- p.133 / Chapter 6.4.1 --- Input Matching Network --- p.133 / Chapter 6.4.2 --- Output Matching Network --- p.136 / Chapter 6.5 --- Design of the LTCC Balanced LNA --- p.140 / Chapter Chapter 7 --- Conclusion and Future Work --- p.148 / References --- p.149 / Author's Publication --- p.152 / Appendix A Even and Odd Modes Analysis for Power Dividers --- p.153 / Appendix B TRL Calibration Technique --- p.162

随着无线通信的蓬勃发展，新的通信标准不断出现，频谱利用率和数据传输速率提高的同时，传输信号的带宽和均峰比也不断增加。此外，多种通信标准共存的现状要求收发机能够在多个载波频率，高效率地传输不同格式的信号。因此，宽带运行和高效的放大高均峰比信号成为了基站功率放大器设计的基本要求。 / Doherty 功率放大器结构简单，增加效率的同时能保持中等线性度，故而受到了广泛关注。本文囊括了三个有关增加Doherty 放大器工作带宽、延展高效率区或提高功率利用因子的创新设计。 / 第一个设计中，复数合路阻抗被用于扩宽Doherty 放大器的高效率区。关于动态阻抗范围，电流比因子和漏极效率的理论分析说明，复数合路阻抗可以当作新的自由度来增加放大器的高效率区。为了验证有关理论，以2GHz 为工作频点，我们使用了相同的基于GaN 工艺的晶体管，分别设计了使用复数合路阻抗和纯实数合路阻抗的Doherty 放大器。连续波测试结果显示，使用复数合路阻抗的Dohety 放大器能够提高9.1dB 的输出回退范围，比基于纯实数合路阻抗的传统设计要高3.6dB。此外，使用单载波、均峰比9.6dB 的WCDMA 信号的测试显示，基于复数合路阻抗的设计在输出功率为33.2dBm 时，其平均漏极效率高达57.4%。 / 第二个设计中使用了随频率变化的复数合路阻抗，通过控制漏极电流，来同时增加Doherty 放大器的工作带宽和高效率区。为了验证有关理论，我们设计了输出功率42dBm、工作带宽1.8-2.2GHz、输出回退区9dB 的Doherty 放大器。连续波测试结果显示，在8.5dB 回退点处，该设计在8.5dB 回退点和饱和输出点的漏极效率分别高达55-59%和69-73%。使用单载波、均峰比9.6dB 的WCDMA 信号的测试显示，该设计在输出功率为33.5dBm 时，其平均漏极效率高达53-58%，邻道抑制比也能保持在-30dBc。 / 最后一个设计中，一种在辅助支路加入变换器的Doherty 结构被用于宽带放大。理论分析显示了该结构能够增加功率利用因子，并提供宽带Doherty 特性。为了验证有关理论，我们设计了输出功率20W、工作带宽1.6-2.4GHz、功率利用因子得到改善的Doherty 放大器。连续波测试结果显示，该设计的功率利用因子高达0.94，所有频点均可得到良好的Doherty 效率特性，该设计在6dB回退点和饱和输出点的漏极效率分别高达55-64%和68-76%。在2GHz 处，使用单载波、均峰比6.6dB 的WCDMA 信号的测试显示，该设计在输出功率为37dBm时，其平均漏极效率高达56%，邻道抑制比低于-37dBc。 / As modern communication system demands higher spectrum efficiency and data rate, new communication standard using complex modulation scheme has emerged and led to transmitting signal with ever-increasing Peak-to-Average Power Ratio (PAPR). Moreover, the co-existence of different standards requires RF transceivers to support signal transmission at multiple carrier frequencies. Therefore, wideband operation and efficient amplification of high PAPR signal are prime requirements for base-station PA design. / For efficiency enhancement, the Doherty Power Amplifier (DPA) [1] has been regarded as the most popular approach due to its circuit simplicity and moderate linearity. Three innovative DPA design techniques relating to the enhancement of operating bandwidth, high efficiency range and power utilization factor (PUF) are proposed in this work. / In the first demonstration, a novel DPA configuration with Complex Combining Load (CCL) is presented to extend the high efficiency range of the amplifier. Theoretical analysis of dynamic load span, current ratio and drain efficiency reveals that complex combining load can offer a new degree of freedom to boost the Output Back-off (OBO) of DPA. For verification, a 2GHz, equal-cell, GaN HEMT-based DPA is simulated, prototyped and measured with both complex and resistive combining loads. Under Continuous Wave (CW) excitation, measurement results show that the CCL DPA can attain an OBO of 9.1 dB which is 3.6 dB higher than that of the RCL design. In addition, by the use of single-carrier WCDMA signal with PAPR of 9.6 dB and at an average output power of 33.2 dBm, the CCL design is found to deliver an average drain efficiency of 57.4%. / The second design presents a novel technique to extend the bandwidth and efficiency range of DPA by the adoption of frequency-varying Complex Combining Load and proper input current control strategy. For verification, a 42 dBm, 1.8-2.2 GHz DPA with OBO of 8.5 dB was designed, built and characterized. Under CW stimulation, a back-off efficiency (8.5 dB) of 55-59% and saturation efficiency of 69-73% were observed over the entire bandwidth. With single carrier WCDMA signal excitation (PAPR of 9.6 dB), an average drain efficiency of 53-58% was obtained at 33.5 dBm average output power and Adjacent Channel Leakage Power Ratio (ACLR) of around -30 dBc. / In the last technique, a novel DPA configuration with auxiliary transformer is presented for broadband operation. Theoretical analysis reveals that the presented design can offer enhanced PUF and wideband Doherty behavior. Based on the proposed theory, a 1.6-2.4 GHz, 20 W DPA with improved PUF is designed, simulated and measured. Under CW excitation, measurement results indicate that the presented DPA can achieve a PUF of 0.94, good Doherty behavior over the entire frequency band with a 6 dB back-off efficiency of 55-64% and saturated efficiency of 68-76%. In addition, by the use of single-carrier WCDMA signal (centered at 2 GHz) with PAPR of 6.6 dB and at an average output power of 37 dBm, an average drain efficiency of 56% is obtained with ACLR of better than -37 dBc. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Fang, Xiaohu. / Thesis (Ph.D.) Chinese University of Hong Kong, 2015. / Includes bibliographical references. / Abstracts also in Chinese.

No description available.

Graduation date: 1998

Standard methodologies exist for testing and characterizing digital circuits but the same cannot be said of analog circuits. Though much theoretical work has been done to model the linear and nonlinear aspects of analog circuits, a firm practical background for the design of testable analog cells has yet to be set. The industry largely looks for solutions wherein some form of built in self-test (BIST) can be incorporated into the analog circuits to make the testing at the manufacturing level easy and accurate. Since the testers in the industry are generally digital, test circuits that use logic levels at the output to make measurements are attractive. This thesis examines the design of such test circuits for one specific analog circuit, the opamp. Test circuits to measure the gain, gain-bandwidth product, phase response and the slew rate of the opamp have been designed and experimental results are presented. The main advantages of these tests are that they are simple, fast, accurate and easy to incorporate in an integrated circuit. / Graduation date: 1994

Thesis (M.S. of electrical engineering)--Washington State University, December 2009. / Title from PDF title page (viewed on Jan. 14, 2010). "Department of Electrical Engineering and Computer Science." Includes bibliographical references (p. 62-63).

Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2004. / Xiaoming Huo, Committee Member ; J. Stevenson Kenney, Committee Member ; Douglas Williams, Committee Member ; Erik Verriest, Committee Member ; G. Tong Zhou, Committee Chair. Vita. Includes bibliographical references (leaves 170-179).