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Tests for detecting faults in analog and mixed-signal circuits have been traditionally derived from the datasheet speci and #64257;cations. Although these speci and #64257;cations describe important aspects of the device, in many cases these application oriented tests are costly to implement and are inefficient in determining product quality. Increasingly, the gap between speci and #64257;cation test requirements and the capabilities of test equipment has been widening. In this work, a systematic method to generate and evaluate alternate tests for detecting parametric faults is proposed. We recognize that certain aspects of analog test generation problem are not amenable to automation. Additionally, functional features of analog circuits are widely varied and cannot be assumed by the test generator. To overcome these problems, an extended device under test (DUT) model is developed that encapsulates the DUT and the DUT speci and #64257;c tasks. The interface of this model provides a well de and #64257;ned and uniform view of a large class of devices. This permits several simpli and #64257;cations in the test generator. The test generator is uses a search-based procedure that requires evaluation of a large number of candidate tests. Test evaluation is expensive because of complex fault models and slow fault simulation techniques. A tester-resident test evaluation technique is developed to address this issue. This method is not limited by simulation complexity nor does it require an explicit fault model. Making use of these two developments, an efficient and automated test generation method is developed. Theoretical development and a number of examples are used to illustrate various concepts that are presented in this thesis.

abstract: The research objective is fully differential op-amp with common mode feedback, which are applied in filter, band gap, Analog Digital Converter (ADC) and so on as a fundamental component in analog circuit. Having modeled various defect and analyzed corresponding probability, defect library could be built after reduced defect simulation.Based on the resolution of microscope scan tool, all these defects are categorized into four groups of defects by both function and location, bias circuit defect, first stage amplifier defect, output stage defect and common mode feedback defect, separately. Each fault result is attributed to one of these four region defects.Therefore, analog testing algorithm and automotive tool could be generated to assist testing engineers to meet the demand of large numbers of chips. / Dissertation/Thesis / M.S. Electrical Engineering 2014

On chip Built In Self Test (BIST) is a cost-effective test methodology for highly complex VLSI devices like Systems On Chip (SoC). This work deals with cost-effective BIST methods and Test Pattern Generation (TPG) schemes in BIST for fault detection and diagnosis of analog circuits. Fault-based testing is used in analog domain due to the applicable test methods/ techniques being general and cost-effective. We propose a novel test method causing the Device Under Test (DUT) to saturate or get out of saturation to detect a fault with simple detection hardware. The proposed test method is best suited for use of existing building blocks in Systems-on-Chip (SoC) for implementation of an on-chip test signal generator and test response analyzer. Test generation for a fault in analog circuit is a compute intensive task. A good test generator produces a highly compact test set with less computational effort without trading the fault coverage. In this context, three new test generation methods viz., MultiDetect, ExpoTan, and MultiDiag for testing analog circuits are presented in this thesis. Testing of analog blocks based on circuit transfer function makes the proposed ATPG methods as general-purpose methods for all kinds of LTI circuits. The principle of MultiDetect method, (i.e., selecting a test signal for which the output amplitude difference between good and faulty circuits is minimum when compared to other test signals in an initial test set), helps in the generation of high quality compacted test set with less fault simulations. The experimental results show that the testing of LTI circuits using MultiDetect technique for the benchmark circuits achieves the required fault coverage with much shorter testing time. The generated test set with MultiDetect method can effectively detect both soft and hard faults and does not require any precision analog signal sources or signal measurement circuits when implemented as Built In Self Test (BIST). Test generation for a list of faults and test set compaction are two different phases in an ATPG process. To build an efficient ATPG, these two phases need to be combined with a technique such that the generated test set is highly compact and efficient with less fault simulations. In this context, a novel test set selection technique known as ExpoTan for testing Linear Time Invariant (LTI) circuits is also presented in this thesis. The test generation problem is formulated with tan-1( ) and exponential functions for identification of a test signal with maximum fault coverage. Identification of a sinusoid that detects more faults results in an optimized test signal set. Fault diagnosis and fault location in analog circuits are of fundamental importance for design validation and prototype characterization in order to improve yield through design modification. In this context, we propose a procedure viz., MultiDiag for generation of a test set for analog fault diagnosis. The analog test generation methods, viz., Max, Rand, and MultiDetect etc., which are based on sensitivity analysis, may fail at times to identify a test signal for locating a fault; because the search for a test signal using these test generation methods is restricted to the limited test signals set. But, the MultiDiag method definitely identifies a test signal, if one exists, for locating a fault.