Internet of Things is expanding to the areas such as healthcare, home management, industrial, agriculture, and becoming pervasive in our life, resulting in improved efficiency, accuracy and economic benefits. Smart sensors with embedded interfacing integrated circuits (ICs) are important enablers, hence, variety of smart sensors are required. However, each type of sensor requires specific interfacing chips, which divides the huge market of sensors’ interface chips into lots of niche markets, resulting in high develop cost and long time-to-market period for each type. Software defined sensor is regarded as a promising solution, which is expected to use a flexible interface platform to cover different sensors, deliver specificity through software programming, and integrate easily into the Internet of Things. In this work, research is carried out on the design and implementations of ultra low power analog interface circuits toward software defined sensors for healthcare services based on Internet of Things.    This thesis first explores architectures and circuit techniques for energy-efficient and flexible analog to digital conversion. A time-spreading digital calibration, to calibrate the errors due to finite gain and capacitor mismatch in multi-bit/stage pipelined converters, is developed with short convergence time. The effectiveness of the proposed technique is demonstrated with intensive simulations. Two novel circuit level techniques, which can be combined with digital calibration techniques to further improve the energy efficiency of the converters, are also presented. One is the Common-Mode-Sensing-and-Input-Interchanging (CSII) operational-transconductance-amplifier (OTA) sharing technique to enable eliminating potential memory effects. The other is a workload-balanced multiplying digital-to-analog converter (MDAC) architecture to improve the settling efficiency of a high linear multi-bit stage. Two prototype converters have been designed and fabricated in 0.13 μm CMOS technology. The first one is a 14 bit 50 MS/s digital calibrated pipelined analog to digital converter that employs the workload-balanced MDAC architecture and time-spreading digital calibration technique to achieve improved power-linearity tradeoff. The second one is a 1.2 V 12 bit 5~45 MS/s speed and power-scalable ADC incorporating the CSII OTA-sharing technique, sample-and-hold-amplifier-free topology and adjustable current bias of the building blocks to minimize the power consumption. The detailed measurement results of both converters are reported and deliver the experimental verification of the proposed techniques.     Secondly, this research investigates ultra-low-power analog front-end circuits providing programmability and being suitable for different types of sensors. A pulse-width- -modulation-based architecture with a folded reference is proposed and proven in a 0.18 μm technology to achieve high sensitivity and enlarged dynamic range when sensing the weak current signals. A 8-channel bio-electric sensing front-end, fabricated in a 0.35 μm CMOS technology is also presented that achieves an input impedance of 1 GΩ, input referred noise of 0.97 Vrms and common mode rejection ratio of 114 dB. With the programmable gain and cut-off frequency, the front-end can be configured to monitor for long-term a variety of bio-electric signals, such as electrooculogram (EOG), electromyogram (EMG), electroencephalogram (EEG) and electrocardiogram (ECG) signals. The proposed front-end is integrated with dry electrodes, a microprocessor and wireless link to build a battery powered E-patch for long-term and continuous monitoring. In-vivo test results with dry electrodes in the field trials of sitting, standing, walking and running slowly, show that the quality of ECG signal sensed by the E-patch satisfies the requirements for preventive cardiac care.    Finally, a wireless multimodal bio-electric sensor system is presented. Enabled by a customized flexible mixed-signal system on chip (SoC), this bio-electric sensor system is able to be configured for ECG/EMG/EEG recording, bio-impedance sensing, weak current stimulation, and other promising functions with biofeedback. The customized SoC, fabricated in a 0.18 μm CMOS technology, integrates a tunable analog front-end, a 10 bit ADC, a 14 bit sigma-delta digital to current converter, a 12 bit digital to voltage converter, a digital accelerator for wavelet transformation and data compression, and a serial communication protocol. Measurement results indicate that the SoC could support the versatile bio-electric sensor to operate in various applications according to specific requirements. / <p>QC 20151221</p>

Due to the increasing demand of broadband capability and reconfigurability for mobile applications, there is an enormous interest to develop appropriate analog receiver front-ends. In this respect, one promising candidate group is the Six-Port-based direct conversion receiver. The presented work focuses on the investigation of Six-Port-based mobile receiver front-ends with their specific systematical signal processing. Thereby, issues of spurious interfering signals which are generated within the down conversion process of such receivers are of special interest. Based on a comprehensive description of the analog signal processing within additive frequency conversion, a reason could be identified why existing Six-Port receivers have not found any practical application in mobile communication yet – the dynamic DC-offset. With this insight compensation techniques were developed to overcome the negative influences of the dynamic DC-offset. Furthermore, this work presents novel Six-Port-based receiver architectures which, on the one hand, keep the advantages of additive mixing systems like: low power consumption, broadband capability and simplicity of implementation especially for mm-wave transmissions. On the other hand, these novel architectures comprise compensation techniques such that systematically generated spurious signals are inherently compensated in the analog part of the receiver. Moreover, the influence of impairments of phase and amplitude within the IQ-branches of a receiver was investigated. The resulting, unwanted IQ-imbalance was shown to be a mixing method (multiplicative or additive) independent spurious effect. It is suggested to compensate for IQ-imbalance in the digital part of the receiver system. This can be realized with the use of adaptive algorithms. The comparison with conventional analog receiver architectures (especially homodyne receivers) with respect to the reception of today’s and future digitally modulated transmission signals indicate the proposed Six-Port-based receiver architectures to be suitable candidates to fulfill the difficult tasks of modern mobile communication.