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We use scaled 3-D thermo-mechanical analogue models to investigate the formation of oroclines (originally linear orogens now curved in map view by buckling about vertical axes). The experimental setup consists of a tank of water (the asthenosphere) on top of which rest hydrocarbon plates (the lithosphere) with strain-softening behaviours and thermo-dependent elasto-plastic properties. An electric heating element below and 4 infrared lights above produce a constant vertical (geo)thermal gradient in the plates. A horizontal piston drives constant plate motion and gives rise to a compressional stress regime. Geometric, kinematic and dynamic variables are calibrated in accordance with a set of scaling laws and proper plate composition. Our results suggest that oroclinal buckling involves the entire lithosphere and cannot be confined to the crust only. A wide range of syn-oroclinal structures developed during buckling, including thin- to thick-skinned thrust belts, transform faults and extensional structures, as well as extensional basins and subduction zones in the lithosphere adjacent to the ribbons. During oroclinal buckling, a thrust belt forms upon complete closure of the interlimb region and is attributable to the trailing orocline limb overthrusting the leading orocline limb. An analogous syn-oroclinal thrust system characterizes the Central Iberian Orocline (CIO) of the Variscan orogen in Iberia where the north limb of the west-convex orocline exposes recumbent north-verging folds while the overriding south limb bears upright to gently north-verging folds. Our results imply that these structures developed during final closure of the CIO, and indicate that the north- and south- limbs of the CIO constitute the leading- and trailing-limbs, respectively, of an orocline that formed by overall northward translation. Modelling of magmatic arcs rotating about vertical axes yields late stage transform faults that bisect the buckling arcs. This outcome is analogous to the Panama Canal fault zone that severs the buckled Panamanian Isthmus. The hinge zones of modeled oroclines are the sites of subduction initiation, similar to subduction initiation of the Caribbean plate beneath the convex to the north, North Panamanian orocline, and of oceanic lithosphere from the Ionian Sea beneath the Calabrian orocline of Sicily. / Graduate / 0372 / gagnonl@uvic.ca

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My claim is that analogue knowledge must be enacted and therefore cannot be documented explicitly, the emphasis lies in the process therefore architecture must address it in such a way. The architecture lends itself to knowledge as a carrier, of both a space for it to enact and to embody its processes and output. The process here is associated with craftsmanship, enduring and evolving where the craftsperson works to delay the image; they do not work to a set goal (the image) but only to further their own knowledge and craft, it is essentially a process of trial and error that evolves the ‘thing’ it is creating. Craft does not hold itself to exquisite products, quite the opposite; its focus is not on the thing it has created but the idea itself, the iterative act, that is craft. When coupled with the practice of analogue knowledge a proposition emerges, an architecture that embodies and addresses this knowledge as a practice archive. A space that pertains to the principals explored in theory however introduces a platform for craftspeople to inhabit and enact. A space that is not ephemeral, where analogue knowledge can endure and evolve as a practice. It becomes an archive not as accumulative practice, but as engaged or performative practice, the performance is the carrier of theory and enactment of knowledge.

A series resonant L-C circuit in which either the inductor or the capacitor is nonlinear and which is excited by a sinusoidal voltage of a fixed frequency may have two steady-state responses. One of these responses is characterized by a high amplitude oscillation; the other by a low one. If the amplitude or frequency of the driving signal is varied slowly, the response may suddenly change or "jump" to the other state. As a result, this phenomenon has been called jump resonance, or ferroresonance. Because the high and low resonant states could be considered as a 0 and 1 basis for digital logic operations, it was the purpose of this work to study the phenomenon and to investigate the possibility of using it in the design of digital logic elements. Equations which exhibit the necessary features were studied on an analogue computer. The results of the study were used as design criteria for the construction of an actual circuit and also as a basis for an approximate analytical study. The analytical study uses the Ritz method to find useful features of the responses. The results of previous users of this method have been extended to include equations with both second derivative coupling and non-symmetrical non-linearities. Based on the above studies, a prototype circuit was designed which has some of the basic properties of conventional flip-flop circuits. One of the main features of this circuit is that it is almost entirely made of reactive components and as a result has very low power consumption. The operation of the circuit is used to verify the validity of the approximations made in both the analogue simulation and the analytical study. The results obtained from the analogue study, the Ritz analysis, and the prototype circuit compare favorably with each other. Some suggestions for future work are given. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate

High-speed digital to analogue converters (DAC), which are optimised for large bandwidth signal synthesis applications, are a fundamental building block and enabling technology in industrial instrumentation, military, communication and medical applications. The spurious free dynamic range (SFDR) is a key specification of high-speed DACs, as unwanted spurious signals generated by the DAC degrades the performance and effectiveness of wideband systems. The focus of this work is to enhance the SFDR performance of high-speed DACs. As bandwidth requirements increase, meeting the desired SFDR performance is further complicated by the increase in dynamic non-linearity. The most widely used architecture in high-speed applications is the current-steering DAC fabricated on CMOS technology. The current source finite output impedance, switch distortion and clock feedthrough are the greatest contributors to dynamic non-linearity and are difficult to improve with the use of MOS devices alone. This research proposes the use of BiCMOS technology that offers high performance, using heterojunction bipolar transistors (HBT) that, when combined with MOS devices, are able to improve on the linearity of the current-steering DAC and hence improve the SFDR. A design methodology is introduced based on BiCMOS fabrication technology to improve SFDR performance and places emphasis on the constraints of modern fabrication processes. A six-bit current-steering application-specific integrated circuit DAC is designed based on the proposed design methodology, which optimises the SFDR performance of high-speed binary weighted architectures by lowering current switch distortion and reducing the clock feedthrough effect to verify the hypothesis experimentally. A novel current source cell is implemented that comprises HBT current switches, negative channel metal-oxide semiconductor (NMOS) cascode and NMOS current source to overcome distortion by specifically enhancing the SFDR for high-speed DACs. A switch driver and low-voltage differential signalling receiver to achieve high-speed DAC performance and their influence on the SFDR performance are designed and discussed. The DAC is implemented using the International Business Machines Corporation (IBM) 8HP silicon germanium (SiGe) BiCMOS 130 nm technology. The DAC achieves a better than 21.96 dBc SFDR across the Nyquist band for a sampling rate of 500 MS/s with a core size of 0.1 mm2 and dissipates just 4 mW compared to other BiCMOS DACs that achieve similar SFDR performance with higher output voltages, resulting in much larger power dissipation. / Dissertation (MEng)--University of Pretoria, 2015. / Electrical, Electronic and Computer Engineering / MEng / Unrestricted

This thesis presents a novel biomimetic cochlea filter which closely resembles the biological cochlea behaviour. The filter is highly feasible for analogue very-large-scale integration (VLSI) circuits, which leads to a micro-watt-power and millimetre-sized hardware implementation. By virtue of such features, the presented filter contributes to a solid foundation for future biologically-inspired audio signal processors. Unlike existing works, the presented filter is developed by taking direct inspirations from the physiologically measured results of the biological cochlea. Since the biological cochlea has prominently different characteristics of frequency response from low to high frequencies, the biomimetic cochlea filter is built by cascading three sub-filters accordingly: a 2nd-order bandpass filter for the constant gentle low-frequency response, a 2nd-order tunable low-pass filter for the variable and selective centre frequency response and a 5th-order elliptic filter for the ultra-steep roll-off at stop-band. As a proof of concept, a biomimetic cochlea filter bank is built to process audio signals, which demonstrates the highly discriminative spectral decomposition and high-resolution time-frequency analysis capabilities similar to the biological cochlea. The filter has simple representation in the Laplace domain which leads to a convenient analogue circuit realisation. A floating-active-inductor circuit cell is developed to build the corresponding RLC ladder for each of the three sub-filters. The circuits are designed based on complementary metal-oxide-semiconductor (CMOS) transistors for VLSI implementation. Non-ideal factors of CMOS transistors including parasitics, noise and mismatches are extensively analysed and consciously considered in the circuit design. An analogue VLSI chip is successfully fabricated using 0.35μ m CMOS process. The chip measurements demonstrate that the centre frequency response of the filter has about 20 dB wide gain tuning range and a high quality factor reaching maximally over 19. The filter has a 20 dB/decade constant gentle low-frequency tail and an over 300 dB/decade sharp stop-band roll-off slope. The measured results agree with the filter model expectations and are comparable with the biological cochlea characteristics. Each filter channel consumes as low as 59.5 ~90μ Wpower and occupies only 0.9 mm2 area. Besides, the biomimetic cochlea filter chip is characterised from a wide range of angles and the experimental results cover not only the auditory filter specifications but also the integrated circuit design considerations. Furthermore, following the progressive development of the acoustic resonator based on microelectro- mechanical systems (MEMS) technology, a MEMS-CMOS implementation of the proposed filter becomes possible in the future. A key challenge for such implementation is the low sensing capacitance of the MEMS resonator which suffers significantly from sensitivity degradation due to the parasitic capacitance. A novel MEMS capacitive interface circuit chip is additionally developed to solve this issue. As shown in the chip results, the interface circuit is able to cancel the parasitic capacitance and increase the sensitivity of capacitive sensors by 35 dB without consuming any extra power. Besides, the chopper-stabilisation technique is employed which effectively reduces the circuit flicker noise and offsets. Due to these features, the interface circuit chip is capable of converting a 7.5 fF capacitance change of a 1-Volt-biased 0.5 pF capacitive sensor pair into a 0.745 V signal-conditioned output while consuming only 165.2μ W power.

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No description available.