Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2005. / Position calculation of mobile objects has challenged engineers and designers for years and is still continuing to do so. There are many solutions available today. Probably the best known and most widely used outdoor system today is the Global Positioning System (GPS). There are very little systems available for indoor use. An absolute positioning system was developed for this thesis. It uses a combination of ultrasonic and Radio Frequency (RF) communications to calculate a position fix in doors. Radar techniques were used to ensure robustness and reliability even in noisy environments. A small mobile robot was designed and built to test and illustrate the use of the system.

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2007. / This thesis examines three reduced complexity algorithms for subspace tracking in the context of radio direction finding. Projection Approximation Subspace Tracking (Yang), the Fast Data Projection Method (Doukopoulos and Moustakides) and OPERA (MacInnes) are presented and compared in terms of performance and efficiency. The algorithms’ performances are contrasted using step changes in direction of arrival, sensitivity to noise and minimum angular discrimination. Their relative efficiencies are examined by comparing their theoretical complexities and by assessing benchmark results. The construction of a PC based signal simulator and direction finding client using the MUSIC algorithm are described. The results of a field assessment of the algorithms are presented, and finally, conclusions regarding the relative merits of the algorithms are drawn.

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2007. / The availability of high density FPGAs has made the use of soft-core processors an attractive proposition for the low volume space market. Soft-core processors combine the power of programmable logic with the ease of use of a conventional processor to provide a highly customisable solution. However, the SRAM FPGAs used as implementation platform are especially susceptable to radiation induced single event upsets, due to the sensitivity of their configuration memory. To safely use these processors in a space environment requires the modification of the processor to safely mitigate these effects. This thesis presents the process followed to develop and test a fault tolerant implementation of an 8-bit PicoBlaze soft-core processor on a Xilinx Spartan-3 SRAM FPGA. A thorough investigation was made into the available methods that can be used to mitigate single event upsets, in order to identify the most suitable ones. Guidelines for the application of SEU mitigation techniques to SRAM FPGAs were proposed. A single event upset simulator was designed and constructed to compare the different techniques. It mimics SEUs by injecting errors into the configuration memory of an FPGA. The results of error injection were used to develop a PicoBlaze implementation with limited overhead, while it still offers a high degree of error mitigation. Three different designs were tested by proton irradiation to verify the protection afforded by the mitigation techniques. It was found that protected designs were more robust. The cross-section of the FPGA was also determined, which can be used with the SEU simulator to predict the dynamic cross-section of designs. The work contained in this thesis demonstrates the use of open-source intellectual property with commercial-off-the-shelf components to develop a robust component for use in the miniature spacecraft market.

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2005. / A process was developed to design and manufacture a dc SQUID magnetometer. Superconductor theory is given as a foundation to explain the Josephson junction. This knowledge is applied to explain the ideal and practical dc SQUID. The design of the dc SQUID is done with inductance calculation formulas. Each step of the manufacturing process is discussed in detail. Many improvements have been made to the process to make each step reproducible. The steps in the manufacturing process that were done in-house are: manufacturing an YBa2Cu3O7−d pellet, depositing the thin film with the pulsed laser deposition process, creating a mask with the UV lithography process, wet etching the circuit and depositing silver contact pads with thermal evaporation. The device is packaged on a printed circuit board device holder and shielded with a mu-metal shield. A test setup is developed to test the final device. Each step in the manufacturing process was successful. The final device did not work, due to oxidisation of the YBa2Cu3O7−d thin film.

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2007. / The use of older and slower protocols has become increasingly difficult to justify due to the rapid pace at which telecommunications are advancing. To keep up to date with the latest technologies, the communications system must be designed to accommodate the transparent insertion of new communications standards in all the stages of a system. The system should, however, also remain compatible with the older standards so as not to demand an upgrade of the older systems. The concept of a software defined radio was introduced to overcome these problems. In a software defined radio system, the functionality of the communications system is defined in software, which removes the the need for alterations to the hardware during technology upgrade. To maintain interoperatibilty, the system must be based on a standardised architecture. This would further allow for enhanced scalability and provide a plug-andplay feature for the components of the system. In this thesis, generic signal processing software components are developed to illustrate the creation of a basic software modem that can be parameterised to comply fully, or partially, to various standards.

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2006. / This thesis investigates the compensation of voltage flicker in an industrial environment. Industrial loads draw progressively less sinusoidal currents. These currents cause non-sinusoidal voltage drop over the line impedance, causing a distorted line voltage. The light output of incandescent electric lighting systems is quadratically proportional to the line voltage, and thus variations in the line voltage cause irritating variations in the output of such systems. Two tools to analyse flicker problems are developed: A USB data logger is built to log measured waveforms to computer hard disk. These data are analysed using a MATLAB implementation of the IEC-specified flicker meter. A converter-based flicker compensator is found to be the only compensator capable of compensating general flicker loads. Such a compensator is developed using the synchronous reference frame filtering technique. Several aspects of the compensator are dealt with in detail including selection of a current control strategy, calculation and implementation of the converter duty cycles and compensation of the various non-idealities in such a controller. Full compensation is contrasted to reactive compensation – the second option being less expensive but also less effective in the compensation of certain loads. The effectiveness of reactive compensation is found to be dependent not only on the type of load, but also on the type of line feeding the flicker load. Three industrial flicker loads are measured and analysed: a three-phase welder, a sawmill and a rock crusher. These loads are simulated, and the compensation proposed confirmed via these simulations. The compensation of the three-phase welder is tested using a hardware scale model. This verified the operation of the proposed flicker compensator in practice.

Thesis (MScEng (Electrical and Electronic Engineering))--Stellenbosch University, 2008. / This thesis describes the design of a high performance, floating-point, standalone embedded system that is appropriate for speech and audio processing purposes. The system successfully employs the Analog Devices TigerSHARC TS201 600MHz floating point digital signal processor as a CPU, and includes 512MB RAM, a Compact Flash storage card interface as non-volatile memory, a multi-channel audio input and output system with two programmable microphone preamplifiers offering up to 65dB gain, a USB interface, a LCD display and a push-button user interface. An Altera Cyclone II FPGA is used to interface the CPU with the various peripheral components. The FIFO buffers within the FPGA allow bulk DMA transfers of audio data for minimal processor delays. Similar approaches are taken for communication with the USB interface, the Compact Flash storage card and the LCD display. A logic analyzer interface allows system debugging via the FPGA. This interface can also in future be used to interface to additional components. The power distribution required a total of 11 different supplies to be provided with a total consumption of 16.8W. A 6 layer PCB incorporating 4 signal layers, a power plane and ground plane was designed for the final prototype. All system components were verified to be operating correctly by means of appropriate testing software, and the computational performance was measured by repeated calculation of a multi-dimensional Gaussian log-probability and found to be comparable with an Intel 1.8GHz Core2Duo processor. The design can therefore be considered a success, and the prototype is ready for development of suitable speech or audio processing software.

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2006. / A radar system observes an aircraft once during each scan of the airspace, and uses these observations to construct a track representing a possible route of the aircraft. However when aircraft interact closely there is the possiblility of confusing the identities of the tracks. In this thesis multiple hypothesis techniques are applied to extract an identity confidence from a track, given a set of possible tracks and observations. The system utilises numerous estimation filters internally and these are investigated and compared in detail. The Identity Confidence algorithm is tested using a developed radar simulation system, and evaluated sucessfully against a series of benchmark tests.

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2005. / This thesis describes techniques proposed for analysing images of borehole cores. We address two problems: firstly, the automated stratigraphic classification of cores based on texture and secondly, the location of thin chromitite layers hidden in pyroxenite cores. Texture features of different rock types are extracted using wavelets, the theory of which provides an intuitive and powerful tool for this purpose. A Bayesian classifier is trained and used to discriminate between different samples. Thin, planar chromitite layers are located using a shortest path algorithm. In order to estimate the physical orientation of any layer found, a sinusoidal curve is fitted. The proposed algorithms were implemented and tested on samples taken from photographed cores. A high success rate was obtained in rock classification, and thin planar layers were located and characterised.

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2007. / This thesis is concerned with the fabrication of high temperature bi-epitaxial grain boundary Josephson junctions for use in superconducting microelectronic circuits. It aims to provide a proof-of-concept manufacturing process which can serve as a basis for future research at the University of Stellenbosch. The work in this thesis integrates ...