In this work, electrical mechanism of Low Temperature Poly-Si Thin-Film Transistors (LTPS TFTs) and Nonvolatile memory TFTs was investigated. First, relationship between trap states in grain boundary and capacitance-voltage (C-V) transfer characteristic curve would be discussed. The experimental results reveal that the C-V curves were a function with the trap state distribution and the measured frequency. The threshold voltage was increased with increasing measured frequency and temperature. Besides, anomalous capacitance was generated in p-channel LTPS TFTs when the device was operated at off-state. In general, the effective capacitance of the LTPS TFTs was only dependent with the overlap area between gate and source/drain under the off-state. However, the experimental results reveal that the off-state capacitance was increased with decreasing measured frequency and/or with increasing measurement temperature. By fitting the curve of drain current versus electric field under off-state region, it was verified that the TAGIDL is consisted of the Pool-Frenkel emission and thermal field emission. In addition, the charge density calculated from the Cch-Vg measurement also the same dependence with electric field. This result demonstrates that the anomalous capacitance is mainly due to the trap-assisted-gate-induced-drain-leakage (TAGIDL). In order to suppress the anomalous capacitance, a band-to-band hot electron (BTBHE) stress was utilized to reduce the vertical electric field between the gate and the drain. The electric field simulation was also performed by ISE-TCAD software. In addition, the degradation mechanism in Nonvolatile memory TFTs under DC stress was discussed. The gate insulator of the Nonvolatile memory TFTs was stacked with oxide-nitride-oxide and the thickness was 40nm-20nm-10nm, respectively. The polarities of the gate insulator were included fresh state, programmed state and erased state. In order to compare the ONO with the STD TFTs, the STD TFTs was also discussed with the same DC stress condition. The experimental results reveal that the degradation phenomenon was not only oxide trapping (Nox) but alsointerface trap (Nit). Besides, the simulation software ISE-TCAD was used to demonstrate these results. This main degradation phenomenon was caused by carrier injecting into oxide which was due to the coulomb force. The Nox and Nit were increased while carrier injected into the gate oxide. On the other hand, there were showed identical degradation mechanism in fresh state and erase state SONOS TFTs under the positive gate bias stress, but in which were not consistent with the program state. In program state, the vertical electric field was released due to trapping electrons in nitride. Therefore, the electric property would slightly improve during the positive gate bias stress and the main degradation mechanism was become to the carrier detrapped from nitride to gate terminal. Beside, the off state C-V curve was slightly increased under the positive gate bias stress in program state. This result was contributed to the electrons trapped in the oxide near the gate insulator edge cause by the electric field corner effect. And then, the electric field corner effect was also verified by the simulation software ISE-TCAD. Finally, the TAGIDL in fresh and erase states is increased with increasing the stress time. On contrary, the situation in program state is decreased with increasing the stress time. These results are contributed to a large number electrons injection into the overlapped insulator region between the gate and S/D and enhancing the band bending in the overlapped region when SONOS TFT is operated at fresh and erase states. However, in program state, the electrons trapped in the nitride are flowed to the gate due to the positive bias.