<p> The subject of this thesis is the design, fabrication and comparative testing of two prototype L-band ferrite digital latching phase shifters. One phaser is a variation of a design published by G.T. Roome and H.A. Hair, "Thin Ferrite Devices for Microwave Integrated Circuits", IEEE Trans. Microwave Theory Tech, vol. MTT-16 pp. 411-420, July 1968. The second design is original and is experimentally and theoretical compared to the first phaser. A comparative study was made because of technological difficulties in making these devices. Insertion losses of 2dB and an order of magnitude less than possible phase shift occurred because of inadequate production facilities. Thus, the comparative study gave a common mode error to the published device and the new device.</p> <p> Also, the theory of ferrite microwave phasers and a discussion of a particular system application which prompted this study are included in this thesis.</p> / Thesis / Master of Engineering (MEngr)

This thesis deals with ultrasound blood flow meter design with emphasis on practical implementation of such device. This medical device is used in ultrasound diagnostic, especially for measuring direction and velocity of blood flow in superficial vessels. This thesis contains consecutive design including description of individual function blocks. Documents for making double-sided printed circuit are included as well.

Department of Curriculum Studies and Education Management / MEd

Low noise low division 2 GHz RF synthesizer integrated circuits (ICs) are conventionally implemented in some form of HBT process such as SiGe or GaAs. The research in this dissertation differs from convention, with the aim of implementing a synthesizer IC in a more convenient, low-cost Si-based CMOS process. A collection of techniques to push towards the noise and frequency limits of CMOS processes, and possibly other IC processes, is then one of the research outcomes. In a synthesizer low N-divider ratios are important, as high division ratios would amplify in-band phase noise. The design methods deployed as part of this research achieve low division ratios (4 ≤ N ≤ 33) and a high phase comparison frequency (>100 MHz). The synthesizer IC employs a first-order fractional-N topology to achieve increased frequency tuning resolution. The primary N-divider was implemented utilising current mode logic (CML) and the fractional accumulator utilising conventional CMOS. Both a conventional CMOS phase frequency detector (PFD) and a CML PFD were implemented for benchmarking purposes. A custom-built 4.4 GHz synthesizer circuit employing the IC was used to validate the research. In the 4.4 GHz synthesizer circuit, the prototype IC achieved a measured in-band phase noise plateau of L( f ) = -113 dBc/Hz at a 100 kHz frequency offset, which equates to a figure of merit (FOM) of -225 dBc/Hz. The FOM compares well with existing, but expensive, SiGe and GaAs HBT processes. Total IC power dissipation was 710 mW, which is considerably less than commercially available GaAs designs. The complete synthesizer IC was implemented in Austriamicrosystems‟ (AMS) 0.35 μm CMOS process and occupies an area of 3.15 x 2.18 mm2. / Dissertation (MEng)--University of Pretoria, 2010. / Electrical, Electronic and Computer Engineering / unrestricted