Embedded SRAM memory is a vital component in modern SoCs. More than 80% of the System-on-Chip (SoC) die area is often occupied by SRAM arrays. As such, system reliability and yield is largely governed by the SRAM's performance and robustness. The aggressive scaling trend in CMOS device minimum feature size, coupled with the growing demand in high-capacity memory integration, has imposed the use of minimal size devices to realize a memory bitcell. The smallest 6T SRAM bitcell to date occupies a 0.1um2 in silicon area. SRAM bitcells continue to benefit from an aggressive scaling trend in CMOS technologies. Unfortunately, other system components, such as interconnects, experience a slower scaling trend. This has resulted in dramatic deterioration in a cell's ability to drive a heavily-loaded interconnects. Moreover, the growing fluctuation in device properties due to Process, Voltage, and Temperature (PVT) variations has added more uncertainty to SRAM operation. Thus ensuring the ability of a miniaturized cell to drive heavily-loaded bitlines and to generate adequate voltage swing is becoming challenging. A large percentage of state-of-the-art SoC system failures are attributed to the inability of SRAM cells to generate the targeted bitline voltage swing within a given access time. The use of read-assist mechanisms and current mode sense amplifiers are the two key strategies used to surmount bitline loading effects. On the other hand, new bitcell topologies and cell supply voltage management are used to overcome fluctuations in device properties. In this research we tackled conventional 6T SRAM bitcell limited drivability by introducing new integrated voltage sensing schemes and current-mode sense amplifiers. The proposed schemes feature a read-assist mechanism. The proposed schemes' functionality and superiority over existing schemes are verified using transient and statistical SPICE simulations. Post-layout extracted views of the devices are used for realistic simulation results. Low-voltage operated SRAM reliability and yield enhancement is investigated and a wordline boost technique is proposed as a means to manage the cell's WL operating voltage. The proposed wordline driver design shows a significant improvement in reliability and yield in a 400-mV 6T SRAM cell. The proposed wordline driver design exploit the cell's Dynamic Noise Margin (DNM), therefore boost peak level and boost decay rate programmability features are added. SPICE transient and statistical simulations are used to verify the proposed design's functionality. Finally, at a bitcell-level, we proposed a new five-transistor (5T) SRAM bitcell which shows competitive performance and reliability figures of merit compared to the conventional 6T bitcell. The functionality of the proposed cell is verified by post-layout SPICE simulations. The proposed bitcell topology is designed, implemented and fabricated in a standard ST CMOS 65nm technology process. A 1.2_ 1.2 mm2 multi-design project test chip consisting of four 32-Kbit (256-row x 128-column) SRAM macros with the required peripheral and timing control units is fabricated. Two of the designed SRAM macros are dedicated for this work, namely, a 32-Kbit 5T macro and a 32-Kbit 6T macro which is used as a comparison reference. Other macros belong to other projects and are not discussed in this document.

This thesis studies the operating characteristics of the boost type battery power modules (BPMs) with series and parallel configurations. Under different operating conditions, the BPMs can be operated at the continuous conduction mode (CCM), the discontinuous conduction mode (DCM), or the hybrid mode with a combination of CCM and DCM. The current distribution and balance discharging among BPMs with different configurations are analyzed in detail. Experiments are carried out to demonstrate the analysis results. Finally, a circuit configuration with arrayed BPMs is proposed for adaptable management and maintenance of a battery power system.

The objective of this thesis is to design a multilevel converter circuit for driving slotless tubular linear generators (STLG) on retrieving renewable energy application. With the changing speeds and reciprocating directions of the movers, the electric energy generated from the STLG will exhibit large fluctuations and is hard to be used directly. Based on machine modeling and mover reference frame projection, a converter circuit and a data acquisition (DAQ)-based drive control scheme have been developed. From the experimental results, the control scheme implemented on the converter circuit can provide acceptable multilevel dc outputs at various operating modes.

This thesis investigates the discharging behavior of serial boost-type battery power modules (BPMs). Even though the BPMs are connected in series to cope with a higher output voltage, all batteries in the BPMs can substantially be operated individually so that can realize the balanced discharging control strategy. By which, the battery currents are scheduled in accordance with their state-of-charges (SOCs).A battery power system formed by 10 boost-type BPMs is built, in which a micro controller is used for detecting the loaded voltages, estimating the SOCs, and controlling the duty ratios of the power converters. Experimental results demonstrate the balanced discharging capability of the serial BPMs. In addition, fault tolerance mechanism is introduced to isolate fault or exhausted batteries and keep the system working with a reduced load.

Charge equalization is a major issue in the service of batteries since they are frequently connected in series to obtain higher output voltage levels for most applications. With series connection, imbalance may happen to the operating batteries during either charging or discharging periods. The imbalance among batteries concerns the operating efficiency and the battery lifetime. The main object of this dissertation is to solve the problem of charge inequality. The importance of charge equalization is first addressed. The problem is demonstrated by experiments of charging/discharging processes. Then, the techniques of battery charging and charge equalization are reviewed. To improve charge equalization, a dynamic balance charging scheme is developed on the basis of buck-boost conversion. The balance charging scheme can be realized by two configurations, that is, ¡§forward allotting¡¨ or ¡§backward allotting¡¨ configurations. The circuits are composed of several duplicated subcircuits and operated by digital control kernel, therefore, they are easy to be applied on battery sets with different numbers of batteries. By dynamically re-allocating the energy drawing from satiated batteries and allotted to hungry ones, the series-connected batteries can reach balance state more efficiently. The balance charging circuits can be employed during off-line or even discharging. However, on observing that the output voltage will vary in a big range when the battery set is discharged, the charge equalization can be integrated with voltage regulation on the output. Evolve from this idea, a balance discharging circuit¡@topology based on multi-winding transformer is proposed. The experiments in this dissertation are carried out on lead-acid batteries, therefore, the reactions and characteristics of lead-acid batteries are discussed. However, the proposed circuits are not restricted to be applied on lead-acid batteries only. Experimental results confirm the theoretical analyses and manifest the effectiveness of the designed circuits.

The thesis aims to the research of active power factor correction (PFC) circuit and develop a DSP-based digital controller. In the thesis, PI controller is the control core for the voltage loop¡Band current loop, and then achieve the function of the power factor correction of boost converter. Finally, we develop a boost converter and connect it to a DSP-based controller to measure the waveforms and verify the power factor correction. Furthermore, the research can be extended to a simulating platform which we can verify the power factor correction by just changing the control law on DSP .

The first topic of this thesis is a voltage boost level clamping circuit for a flash memory which utilizes an implicit feedback loop as well as MOS transistors with different threshold voltages. The proposed design can be added to charge pumps to stabilize the output voltage. The unwanted output voltage spikes introduced by the linear pumping ratio are prevented. Not only are possible damages to memory cores avoided, the power disspation is reduced in contrast with prior regulator methods. The second topic is a switch-current 3-bit CMOS wideband random signal generator, which utilizes a digital normalizer to flatten the distribution of the probability in the entire range of B parameter. The ¡§colored¡¨ random numbers problem in prior designs is resolved. In addition, the coefficients of the proposed design are dynamically adjustable.

This thesis presents a novel configuration of battery power by the outputs with serial connection of battery power modules (BPMs) for high voltage level loads. As compared to the conventional application of series-connected battery bank, this configuration operates the BPMs individually, and thus has the advantages of flexible control, convenient maintenance, and easily favorable battery management. The associated converter is equipped to a single battery pack, so that has lower component stresses leading to a higher circuit efficiency. The operation and the design of a lead-acid battery power with series boost-typed BPMs are illustrated. The operation and the design of the converter are illustrated. The control of the power converters is accomplished by a complex programmable logic device (CPLD). To improve the converter efficiency, the technique of synchronous rectification is introduced. For the BPMs designed for discontinuous conduction mode (DCM) operation, charge equalization can be automatically achieved under the same duty-ratio, but is adequate only for batteries with a small difference. On the other hand, charge equalization for the BPMs with continuous conduction mode (CCM) can easily be accomplished by regulating the duty-ratios of the converters.

Worldwide, renewable energy systems are booming with reliable distributed generation (DG) technologies to help fuel increasing global energy consumption and mitigate the corresponding environmental problems. High cost and low efficiency are major problems for such systems using traditional buck inverters with line-frequency transformers. This thesis has proposed a novel single-phase single-stage buck-boost inverter suitable for cost-effective small DG systems. The inverter was analyzed from the angle of energy exchange and transfer with two current control schemes, DCM and CCM. Sinusoidal PWM (SPWM) control method, based on DCM, was discussed in details with steady state analyses, computer simulations, and laboratory tests. A concise model with underlying equations was derived to represent the physical behavior of proposed inverter. Closed-loop SPWM control was simulated and verified to have fast dynamic response and good tracking performance with robustness and insensitivity to dc input fluctuations, ac grid variations, and component parametric uncertainties. Other control strategies were also investigated from the critical DCM, CCM, or energy approach to either increase the fundamental output or further improve the performance. Comparisons demonstrated that SPWM was preferred control method with low output THD, reduced switching losses, and simple implementation. Therefore, it is concluded the proposed inverter provides a low-cost and high-efficient solution for small DG systems with low component count, minimal dc and ac filtering requirements, and improved performance.

Embedded SRAM memory is a vital component in modern SoCs. More than 80% of the System-on-Chip (SoC) die area is often occupied by SRAM arrays. As such, system reliability and yield is largely governed by the SRAM's performance and robustness. The aggressive scaling trend in CMOS device minimum feature size, coupled with the growing demand in high-capacity memory integration, has imposed the use of minimal size devices to realize a memory bitcell. The smallest 6T SRAM bitcell to date occupies a 0.1um2 in silicon area. SRAM bitcells continue to benefit from an aggressive scaling trend in CMOS technologies. Unfortunately, other system components, such as interconnects, experience a slower scaling trend. This has resulted in dramatic deterioration in a cell's ability to drive a heavily-loaded interconnects. Moreover, the growing fluctuation in device properties due to Process, Voltage, and Temperature (PVT) variations has added more uncertainty to SRAM operation. Thus ensuring the ability of a miniaturized cell to drive heavily-loaded bitlines and to generate adequate voltage swing is becoming challenging. A large percentage of state-of-the-art SoC system failures are attributed to the inability of SRAM cells to generate the targeted bitline voltage swing within a given access time. The use of read-assist mechanisms and current mode sense amplifiers are the two key strategies used to surmount bitline loading effects. On the other hand, new bitcell topologies and cell supply voltage management are used to overcome fluctuations in device properties. In this research we tackled conventional 6T SRAM bitcell limited drivability by introducing new integrated voltage sensing schemes and current-mode sense amplifiers. The proposed schemes feature a read-assist mechanism. The proposed schemes' functionality and superiority over existing schemes are verified using transient and statistical SPICE simulations. Post-layout extracted views of the devices are used for realistic simulation results. Low-voltage operated SRAM reliability and yield enhancement is investigated and a wordline boost technique is proposed as a means to manage the cell's WL operating voltage. The proposed wordline driver design shows a significant improvement in reliability and yield in a 400-mV 6T SRAM cell. The proposed wordline driver design exploit the cell's Dynamic Noise Margin (DNM), therefore boost peak level and boost decay rate programmability features are added. SPICE transient and statistical simulations are used to verify the proposed design's functionality. Finally, at a bitcell-level, we proposed a new five-transistor (5T) SRAM bitcell which shows competitive performance and reliability figures of merit compared to the conventional 6T bitcell. The functionality of the proposed cell is verified by post-layout SPICE simulations. The proposed bitcell topology is designed, implemented and fabricated in a standard ST CMOS 65nm technology process. A 1.2_ 1.2 mm2 multi-design project test chip consisting of four 32-Kbit (256-row x 128-column) SRAM macros with the required peripheral and timing control units is fabricated. Two of the designed SRAM macros are dedicated for this work, namely, a 32-Kbit 5T macro and a 32-Kbit 6T macro which is used as a comparison reference. Other macros belong to other projects and are not discussed in this document.