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Design and Discrete Optimization of BIBO Stable FRM Digital Filters Incorporating IIR Digital Interpolation SubfiltersBokhari, Syed 06 1900 (has links)
Digital filters having sharp transition band play a vital role in modern digital signal processing (DSP) applications. Emerging technologies require digital filters to be both computationally efficient in software/hardware realizations. This thesis is concerned with the design and structural-level optimization of sharp transition band digital filters employing the well known frequency response masking (FRM) approach. Unlike the conventional finite impulse response (FIR) based FRM approach, the FRM technique used in this thesis incorporates infinite impulse response (IIR) digital interpolation subfilters, thereby reducing the overall filter order that results in a reduction of hardware complexity. Two realization methods are discussed in this thesis, namely, the bilinear-lossless-discrete-integrators (bilinear-LDI) digital filter design technique, and the lattice wave digital filter (lattice WDF) digital filter design technique.
Diversity controlled (DC) genetic algorithm (GA) is employed to optimize both types of IIR based FRM digital filters over the efficient canonical signed digit (CSD) multiplier coefficient space. DCGAs represent FRM digital filters by a binary chromosome and proceed from a population pool of candidate chromosomes to future generations in order
to arrive at the desired FRM digital filter satisfying the design specifications. A novel cost-function is used that allows the DCGA to simultaneously optimize both the amplitude-frequency and group-delay frequency response. A fast convergence speed has been observed. / Communications
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Design and Discrete Optimization of BIBO Stable FRM Digital Filters Incorporating IIR Digital Interpolation SubfiltersBokhari, Syed Unknown Date
No description available.
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Optimal, Multiplierless Implementations of the Discrete Wavelet Transform for Image Compression ApplicationsKotteri, Kishore 12 May 2004 (has links)
The use of the discrete wavelet transform (DWT) for the JPEG2000 image compression standard has sparked interest in the design of fast, efficient hardware implementations of the perfect reconstruction filter bank used for computing the DWT. The accuracy and efficiency with which the filter coefficients are quantized in a multiplierless implementation impacts the image compression and hardware performance of the filter bank. A high precision representation ensures good compression performance, but at the cost of increased hardware resources and processing time. Conversely, lower precision in the filter coefficients results in smaller, faster hardware, but at the cost of poor compression performance. In addition to filter coefficient quantization, the filter bank structure also determines critical hardware properties such as throughput and power consumption.
This thesis first investigates filter coefficient quantization strategies and filter bank structures for the hardware implementation of the biorthogonal 9/7 wavelet filters in a traditional convolution-based filter bank. Two new filter bank properties—"no-distortion-mse" and "deviation-at-dc"—are identified as critical to compression performance, and two new "compensating" filter coefficient quantization methods are developed to minimize degradation of these properties. The results indicate that the best performance is obtained by using a cascade form for the filters with coefficients quantized using the "compensating zeros" technique. The hardware properties of this implementation are then improved by developing a cascade polyphase structure that increases throughput and decreases power consumption.
Next, this thesis investigates implementations of the lifting structure—an orthogonal structure that is more robust to coefficient quantization than the traditional convolution-based filter bank in computing the DWT. Novel, optimal filter coefficient quantization techniques are developed for a rational and an irrational set of lifting coefficients. The results indicate that the best quantized lifting coefficient set is obtained by starting with the rational coefficient set and using a "lumped scaling" and "gain compensation" technique for coefficient quantization.
Finally, the image compression properties and hardware properties of the convolution and lifting based DWT implementations are compared. Although the lifting structure requires fewer computations, the cascaded arrangement of the lifting filters requires significant hardware overhead. Consequently, the results depict that the convolution-based cascade polyphase structure (with "<i>z</i>₁-compensated" coefficients) gives the best performance in terms of image compression performance and hardware metrics like throughput, latency and power consumption. / Master of Science
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Design of Low Cost Finite-Impulse Response (FIR) Filters Using Multiple Constant Truncated MultipliersZhang Jian, Jun-Hong 10 September 2012 (has links)
Finite impulse response (FIR) digital filters are frequently used in many digital signal processing and communication applications, such as IS-95 CDMA, Digital Mobile Phone Systems (D-AMPS), etc. FIR filter achieves the frequency response of system requirement using a series of multiplications and additions. Previous papers on FIR hardware implementations usually focus on reducing area and delay of the multiple constant multiplications (MCM) through common sub-expression elimination (CSE) in the transpose FIR filter structure. In this thesis, we first perform optimization for the quantization of FIR filter coefficients that satisfy the target frequency response. Then suitable encoding methods are adopted to reduce the height of the partial products of the MCM in the direct FIR filter structure. Finally, by jointly considering the errors in the truncated multiplications and additions, we can design the hardware-efficient FIR filter that meets the bit accuracy requirement. Experimental results show that although CSE in the transpose FIR structure can reduce more area in MCM, the direct form takes smaller area in registers. Compared with previous approaches, the proposed FIR implementations with direct form has the minimum area cost.
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