This thesis addresses the design and implementation of a dual-mode channel decoder for two advanced wireless communication systems. One of the targetsystems is the digital video broadcasting for hand-held terminals (DVB-H) , and the other one is Worldwide Interoperability for Microwave Access (WiMAX) system based on the recently approved IEEE 802.16e. Both standards promise to deliver high data bandwidth within very broad regions. The error control coding schemes of both standards are all built on the similar concatenated code, with the exception of the way of data interleaving. Therefore, the decoders for both standards can be highly integrated. To achieve the low-cost and low-power decoder, this thesis proposes several novel design ideas. First, a fast dynamic multiple path convergence mechanism is proposed for the design of Viterbi decoder module, which can determine the survivor path at earlier stage. Furthermore, a new modified forward path prediction method is also presented which can efficiently predict the possiblesurvivor path such that the number of memory operations during the trace-back canbe significantly reduced. The proposed methodology can reduce up to 50% to 80%of memory operations compared with the best prediction scheme in the literature at high signal-to-noise ration. Secondly, for the block deinterleaver adopted by IEEE 802.16. a new multi-bank architecture is proposed by properly splitting and allocating the input data to suitable bank. The proposed block deinterleaver can be highly integrated with the byte-level convolutional deinterleaver adopted by the DVB-H standard by realizing the multiply First-In-First-Out (FIFO) data branches as the circular buffer. The other salient feature of the proposed dual-mode decoder is that all the major data storage units can all be realized by single-port memory such that the overall cost can be highly reduced.

In this thesis, a highly efficient implementation of the channel decoder for terrestrial digital video broadcast (DVBT) standard is proposed. DVB-T channel decoder is mainly composed of four major modules including the inner Viterbi decoder, outer Reed-Solomon decoder and inner and outer de-interleaver modules which all require significant amount of intermediate data storage. The main contribution of this thesis is to propose suitable architectural solution for each individual module to achieve efficient realization of the data storage mostly by single-port memory blocks which can lead to the reduction of silicon area and the dynamic power dissipation. For the outer convolutional deinterleaver module, a special address generator has been proposed such that the data deinterleaver path can be merged and implemented as three memory blocks. For the inner symbol deinterleaver module, a lookahead technique has been applied to the design of address generator that can generate valid deinterleaving address each cycle to avoid the buffering problem. In addition, a novel deinterleaver memory partitioning architecture is proposed such that the entire deinterleaver can be built on four single-port memory banks. These four modules have been verified and integrated as a robust channel decoder silicon intellectual property (IP). Our implementation result shows that the core area of entire DVB-T channel decoder IP (Intellectual Property) can be realized in less than 6.8 mm2 in 0.18-µm TSMC technology.

In this thesis, we introduce a methodology to design and implement a Homeplug1.0 channel decoder that is completely conforming to Homeplug 1.0 specifications definedin HomePlug Power-line Alliance Standard (HPA) including Reed-solomon decoding,Viterbi decoding, punctured ,and de-interleaving technologies. Further, by using MATLAB/Simullink software, Xilinx System Generator, Xilinx Alliance tools, XilinxISE and Modelsim SE software, we build up a transceiver platform to simulate and analyze the performance of the power-line channel decoder based on FPGA hardware implementation. The hardware can be used directly in practical Homeplug 1.0 systems.

With the approach of the era of digital TV system around the world, how to grasp the design techniques of the receiver of the DVB-T has become a very important topic. The goal of this thesis is to pursue a highly optimized VLSI architecture compatible to the channel decoding standard of the DVB-T protocol. The channel decoding scheme adopted in DVB-T is based on the concatenated code; which is comprised of an inner Viterbi decoder, outer Reed-Solomon decoder and inner and outer de-interleaver modules. These modules all require a significant amount of data storage space, therefore the main feature of the proposed channel decoder architectures is to realize the data storage based on RAM instead of registers. This approach can lead to the reduction of silicon area and the dynamic power dissipation compared with the shift register based architecture. In order to achieve this, in the design of Viterbi module, the popular register-exchange and trace-back techniques used for the detection of the survivor path has been combined for the survivor memory management unit. As for the design of Reed-Solomon decoder, it is designed based on the modified inverse-free Berlekamp-Massey algorithm. A novel finite field constant multiplier architecture has been proposed which can reduce the required gate count of the multipliers by 20%. For outer convolutional deinterleaver, a specific address generator has been designed such that the data deinterleaver path can be merged and implemented as two memory blocks. For inner symbol deinterleaver, a lookahead technique has been applied to the design of address generator and deinterleaver memory has been reduced by a half compared with those in the literature. These four modules have been verified and integrated as robust channel decoder silicon IP. The related models used for IP integration and verification have also been provided. The prototyping on the FPGA has been tested to satisfy the requirement of the spec.

With the enormous growing applications of mobile communications, how to reduce the power dissipation of wireless communication has become an important issue that attracts much attention. One of the key techniques to achieve low power transmission is to develop a powerful channel coding scheme which can perform good error correcting capability even at low signal-to-noise ratio. In recent years, the trend of the error control code development is based on the iterative decoding algorithm which can lead to higher coding gain. Especially, the rediscovery of the low-density parity-check code ¡]LDPC¡^has become the most famous code after the introduction of Turbo code since it is the code closest to the well-know Shannon limit. However, since the block size used in LDPC is usually very large, and the parity matrix used in LDPC is quite random, the hardware implementation of LDPC has become very difficult. It may require a significant number of arithmetic units as well as very complex routing topology. Therefore, this thesis will address several design issues of LDPC decoder. First, under no SNR estimation condition, some simulation results of several LDPC architectures are provided and have shown that some architectures can achieve close performance to those with SNR estimation. Secondly, a novel message quantization method is proposed and applied in the design LDPC to reduce to the memory and table sizes as well as routing complexity. Finally, several early termination schemes for LDPC are considered, and it is found that up to 42% of bit node operation can be saved.