Chiplets have become an increasingly popular technology for extending Moore's Law and improving the reliability of integrated circuits. They do this by placing several small, interacting chips on an interposer rather than the traditional, single chip used for a device. Like any other type of integrated circuit, chiplets are in need of a physical layer of security to defend against hardware Trojans, counterfeiting, probing, and other methods of tampering and physical attacks. Power distribution networks are ubiquitous across chiplet and monolithic ICs, and are essential to the function of the device. Thus, we propose a method of fingerprinting transient signals within the PDN to identify individual chiplet systems and physical-layer threats against these devices. In this work, we describe a Python-wrapped HSPICE model we have built to automate testing of our proposed PDN fingerprinting methods. We also document the methods of analysis used- wavelet transforms and time-domain measurements- to identify unique characteristics in the voltage response signals to transient stimuli. We provide the true positive and false positive rates of these methods for a simulated lineup of chips across varying operating conditions to determine uniqueness and reliability of our techniques. Our simulations show that, if characterized at varying supply voltage and temperature conditions in the factory, and the sensors used for identification meet the sample rates and voltage resolutions used in our tests, our protocol provides sufficient uniqueness and reliability to be enrolled. We recommend that experimentation be done to evaluate our methods in hardware and implement sensing techniques to meet the requirements shown in this work.

<p dir="ltr">The adoption of Heterogeneous Integration (HI) technologies in semiconductor packaging to build 2.5D/3D structures has led to increased power densities and material heterogeneity. These structures place a new burden on thermal and mechanical design. Additionally, these structures allow for significantly increased physical design freedom. With more possible layout options as well as tougher thermal constraints, new specialized tools are required to accelerate this type of design.</p><p dir="ltr">To address this problem using traditional finite element analysis Stack3D is presented. Stack3D is a steady-state thermal-mechanical geometry modeling and analysis platform for advanced packaging early design exploration. It is a finite element simulator developed from scratch in Matlab complete with symbolic geometry representation, automatic meshing, chip power map support, and sparse matrix acceleration.</p><p dir="ltr">After the development of Stack3D, methods for further accelerating the simulation process at the cost of solution accuracy were examined. Neural networks were selected as an engine for this task based on their millisecond evaluation time. In order to choose between the training paradigms of Physics Informed and Data Driven neural networks, a series of benchmarks were run to identify Data Driven networks as ideal candidates for steady state heat conduction.</p><p dir="ltr">Last, the first neural network model for fully generalized steady state heat conduction of 3D packages is developed. This is made possible by using the solution to the partial differential equation governing steady state heat conduction and casting the problem into an image-to-image translation framework. After accounting for the third spatial dimension, this allows the use of cutting edge image processing network for the heat conduction problem. After training, the network was able to run tens of thousands of simulations with an average of 0.53\% error and 0.0035 seconds per simulation.</p>