Power electronics is a constantly growing and demanding technical field. Consumer demand and developing technologies have made the improvement of power density a primary emphasis of research for this area. Power semiconductors present some of the major challenges for increasing system level power density due to high loss density and interconnection requirements. Advanced cooling schemes, such as double-sided, forced liquid convection or multi-phase flow, can be implemented with non-wire bond packaging to improve thermal management while maintaining proper electrical performance. Embedded power is one such packaging technology, which provides a compact structure for interface of power semiconductor to fluid flow. The objective of this work was to identify the potential of implementing embedded power packaging with double-sided forced liquid convection. Physics based, electro-thermal models were first used to predict the improvement in heat transfer of double-sided, forced liquid convection with embedded power packaging over single-sided liquid cooled wire bond based packaging. A liquid module test bed was designed and constructed based on the electro-thermal models, which could be interfaced with high power MOSFET based samples implementing various packaging technologies. Experiments were used to verify the model predictions and identify practical limitations of high flow rate, double-sided liquid cooling with embedded power. An improvement of 45% to 60% in total junction to case thermal resistance is shown for embedded power packaging with double-sided liquid cooling for water flow rates between 0.25 and 4.5 gal/min. / Master of Science

Abstract This thesis is mainly aimed to the study the basic physical properties of different flux, and the combination with semiconductor packaging of 0.6mm Sn96.5/Ag3.0/Cu0.5 (SAC305) big solder ball, and 0.3mm Sn98.5/Ag1.0/Cu0.5 (SAC105) small solder ball. Big solder ball was proceeded with shear stress test, pull ball test, and tray drop test. However small solder ball was proceeded with shear stress test, pull ball test, zone shear solder balls test and board level drop test. After experiments, samples of different flux, the effect of solder strength and mechanical properties were received and discussed. And failure modes were observed by high-power microscope, SEM and OM. The experimental result shows that the flux doesn¡¦t have direct relationship with the point of welding strong and weak, the point of welding strong and weak is determined by the metal¡¦s characteristics. However, the less of residual flux is, the higher the solder balls shearing force as well as pulling force are. As for the more of residual more of flux, after aged processing, some solder balls have the phenomenon of missing from the IMC layer. And the difference of the residual flux will affect the various failure modes of zone shear solder balls. From board level drop test, the majority of failure modes is pad peeling at the corner of test board side for all test flux, and the remaining failure modes exhibit solder fractured and IMC layer broken. Therefore, the judgement of the residual flux is a very important key factor for the semiconductor packaging. It doesn¡¦t have the direct correlation with the reliability of final products. Keywords: Lead Free, Solder Ball, Flux, Semiconductor Packaging, Tests.

Submitted by JOSIANE SANTOS DE OLIVEIRA (josianeso) on 2018-10-01T11:47:12Z No. of bitstreams: 1 Márcio Rafael Stracke_.pdf: 1667083 bytes, checksum: 7f8c37d9c5a822527980feaaec50278e (MD5) / Made available in DSpace on 2018-10-01T11:47:13Z (GMT). No. of bitstreams: 1 Márcio Rafael Stracke_.pdf: 1667083 bytes, checksum: 7f8c37d9c5a822527980feaaec50278e (MD5) Previous issue date: 2018-06-06 / HT Micron / Com o avanço da microeletrônica, cada vez mais surgem dispositivos eletrônicos portáteis. Isso traz diversos desafios à cadeia de semicondutores, desde o projeto, no desenvolvimento de circuitos integrados menores e mais eficientes até o encapsulamento, uma vez que os componentes tem ficado menores, mais finos e com um número maior de pinos de entrada e saída. Esses desafios estão presentes em todos os processos de fabricação de um chip e podemos citar a moldagem como um processo crítico em especial. A tecnologia de moldagem por transferência, que está consolidada e é a principal utilizada neste processo, necessita de cuidados especiais na otimização de seus parâmetros e materiais, tendo em vista os fatores citados e a consequente redução do diâmetro dos fios que realizam a interconexão do die com o substrato. Neste cenário, o wire sweep, que é o arraste destes fios de solda devido ao escoamento do encapsulante, acaba se tornando um problema, já que perdas no processo de moldagem implicam em sucatear o componente. A taxa de falhas devido a este tipo de falha podem chegar a 2,5%, segundo estudos de grandes fabricantes da cadeia de semicondutores divulgado em (SANDGREN; ROTH, 2004). Neste trabalho foi simulado o processo de moldagem de memórias DRAM com encapsulament do tipo BOC BGA, utilizando o módulo de FSI do software COMSOL. Os resultados da razão de wire sweep obtidos na simulação ficaram dentro do intervalo da média com um desvio padrão, na comparação com os valores reais medidos em peças fabricadas na condição simulada, tendo como erro máximo 15,26%. / The advancement of microelectronics makes more and more portable electronic devices emerge in our daily lives. This brings a number of challenges to the semiconductor chain, from design, to the development of smaller and more efficient integrated circuits to encapsulation, since the components have become smaller, thinner, and with a larger number of input and output pins. These challenges are present in all chip fabrication processes and we can define molding as a critical process in particular. The transfer molding technology, which is consolidated and the main one used in this process, requires special care in the optimization of its parameters and materials, since there are more and shorter wires realizing the connection between the die and the substrate. The wire sweep, which is the entrainment of the wires due to the flow of the mold compound, becomes a problem, since losses in the molding process imply scrapping the component. The failure rate due to this type of failure can reach 2.5%, according to studies by major semiconductor chain manufacturers disclosed in (SANDGREN; ROTH, 2004). In this project the DRAM memory molding process with BOC BGA encapsulation type was simulated using the FSI module in COMSOL software. Results of wire sweep ratio obtained are within the average adding or subtracting one standard deviation and the maximum error rate ranging was 15.26% considering manufactured boards using the simulation parameters.

Wide bandgap (WBG) semiconductor devices are becoming increasing popular in power electronics applications. However, WBG semiconductor devices generate a substantial amount of conducted electromagnetic interference (EMI) compared to silicon (Si) devices due to their ability to operate at higher switching frequencies, higher operating voltages and faster slew rates. This thesis explores and analyzes EMI mitigation techniques that can be applied to a power module architecture at the packaging level. In this thesis, the EMI footprint of four different module architectures is measured experimentally. A time domain LTspice simulation model of the experimental test setup is then built. The common mode (CM) EMI emissions that escape the baseplate of the module into the converter is then examined through the simulation. The simulation is used to explore the CM noise footprint of eight additional module architectures that were found in literature. The EMI trends and the underlying mitigation principle for the twelve modules is explained by highlighting key differences in the architectures using common mode equivalent modelling and substitution and superposition theorem. The work aims to help future module designers by not only comparing the EMI performance of the majority of module architectures available in literature but by also providing an analysis methodology that can be used to understand the EMI behavior of any new module architecture that has not been discussed. Although silicon carbide (SiC) modules are used for this study, the results are applicable for any WBG device. / M.S. / As society moves towards the electric grid of the future, there have been increasing calls for high efficiency, high power density, and low electromagnetic interference (EMI) power electronic converters. EMI is a big problem when using wide-bandgap (WBG) devices as these devices can switch very quickly and handle higher voltages when compared to silicon devices. In this study, ways to reduce EMI in a WBG power module through twelve different types of packaging are explored. Four WBG power modules are designed and fabricated in the lab, whereas a simulation model was created to study the EMI behavior of the remaining eight power module. The EMI behavior of these modules is explained using common mode (CM) equivalent modeling and substitution and superposition theorem. This study is important because WBG devices are becoming more and more popular in power electronic applications. The author hopes the findings and analysis presented in this paper can help future module designers reduce the EMI footprint of modules they design.

<p dir="ltr"><i>The high heat fluxes generated in electronic devices must be effectively diffused through </i><i>the semiconductor substrate and packaging layers to avoid local, high-temperature “hotspots” </i><i>that govern long-term device reliability. In particular, advanced semiconductor packaging </i><i>trends toward thin form factor products increase the need for understanding and improving </i><i>in-plane conduction heat spreading in anisotropic materials. Furthermore, predicting thermal </i><i>transport in vertical stacks of thinned and bonded die hinges on accurately characterizing </i><i>unknown buried interfacial thermal resistances. The design of semiconductor thermal packaging </i><i>solutions is hence limited by the functionality and accuracy of metrology available </i><i>for thermal properties characterization of engineered anisotropic heat spreading materials </i><i>and buried interfaces. This work focuses on the development of two separate innovative </i><i>metrology techniques for characterizing in-plane thermal properties of both isotropic and </i><i>anisotropic materials, and the measurement of low thermal interfacial resistances embedded </i><i>in stacks of semiconductor substrates.</i></p><p dir="ltr"><i>In the first portion of this thesis, a new measurement technique is developed for characterizing </i><i>the isotropic and anisotropic in-plane thermal properties of thin films and sheets, </i><i>as an extension of the traditional Ångstrom method and other lock-in thermography techniques. </i><i>The measurement leverages non-contact infrared temperature mapping to quantify </i><i>the thermal response to laser-based periodic heating at the center of a suspended thin film </i><i>sample. This novel data extraction method does not require precise knowledge of the boundary </i><i>conditions. To validate the accuracy of this technique, numerical models are developed </i><i>to generate transient temperature profiles for hypothetical anisotropic materials with known </i><i>properties. The resultant temperature profiles are processed through a fitting algorithm to </i><i>extract the in-plane thermal conductivities, without the knowledge of the input properties </i><i>to the forward model. Across a wide range of in-plane thermal conductivities, these results </i><i>agree well with the input values. The limits of accuracy of this technique are identified based </i><i>on the experimental and sample parameters. Further, numerical simulations demonstrate </i><i>the accuracy of this technique for materials with thermal conductivities from 0.1 to 1000 W </i><i>m</i><i>−1 </i><i>K</i><i>−1</i><i>, and material thicknesses ranging from 0.1 to 10 mm. This technique effectively</i> <i>measures anisotropy ratios up to 1000:1. Data from multiple heating frequencies can be </i><i>combined to fit for a single set of thermal properties (independent of frequency), which improves </i><i>measurement sensitivity as the thermal penetration depth varies across frequencies. </i><i>The post-processing algorithm filters out regions within the laser absorber and heat sink to </i><i>eliminate regions in the sample domain with boundary effects. Based on these guidelines, </i><i>experiments demonstrate the accuracy of this measurement technique for a wide range of </i><i>known isotropic and anisotropic heat spreading materials across a thermal conductivity range </i><i>of 0.3 to 700 W m</i><i>−1 </i><i>K</i><i>−1</i><i>, and in-plane anisotropy ratios of 30:1. These steps contribute </i><i>towards standardization of this measurement technique, enabling the development and characterization </i><i>of engineered heat spreading materials with desired anisotropic properties for </i><i>various applications.</i></p><p dir="ltr"><i>The second portion of this thesis focuses on characterization of thermal resistances across </i><i>“buried” interfaces that are challenging to characterize in situ due to their low relative magnitude </i><i>and embedded depth within a material stack. In particular, we target characterization </i><i>of interfaces that are buried deeper than the thermal penetration depth of available transient </i><i>measurement techniques, such as thermoreflectance, but have low thermal resistances </i><i>that prohibit the use of steady-state techniques, such as the reference bar method, due to </i><i>the very high temperature gradients that would be necessary resolve the resistances, among </i><i>other sample preparation challenges. This work develops a technique for the non-destructive </i><i>characterization of such deeply buried interfaces having thermal contact resistances of the </i><i>order of 0.001 cm</i><i>2</i><i>K/W. Two different embodiments of the measurement approach are first </i><i>assessed before down-selecting to a single experimental implementation. The working principle </i><i>for both embodiments includes a combination of non-contact periodic heating and </i><i>thermal sensing to measure the transient temperature response of a two-layer stack of materials </i><i>with a bonded interface of unknown thermal resistance. The approaches aim to </i><i>eliminate the preparation requirement of cutting samples to investigate their temperature in </i><i>cross-section. In the first embodiment, the sample stack is heated periodically at the center </i><i>of the sample, and cooled at the periphery, to create a radial temperature gradient. The </i><i>second embodiment involves generating a one-dimensional temperature gradient across the </i><i>stack by periodic heating of one face and steady cooling of the other face. The corresponding </i><i>ing amplitude and phase delay of the temperature responses are used to fit for the thermal </i><i>interfacial resistance, assuming a time-periodic solution for the heat diffusion equation for </i><i>a system with periodic heating. Numerical models developed for both approaches simulate </i><i>the transient temperature profiles across a two-layer bonded silicon stack of known thermal </i><i>properties, and enable an assessment of both approaches. The one-dimensional (1D) gradient </i><i>approach is found to have higher sensitivity and measurable signal compared to the </i><i>radial spreading approach, at the same mean temperature of the sample. </i></p><p dir="ltr"><i>Based on this 1D gradient concept, an experimental facility is developed, which includes </i><i>a IR-transparent heat sink, laser-based heating, and two IR temperature sensors for noncontact </i><i>temperature measurement of both sides of the sample. The unique IR transparent </i><i>heat sink design allows for simultaneous cooling and non-contact temperature measurement </i><i>of the bottom surface of the sample. An inverse fitting method is developed to extract </i><i>the thermal resistances using the steady periodic temperature amplitude and phase delay </i><i>across the thickness of the material. Thermal data generated using numerical simulations, </i><i>along with the data fitting method, is first leveraged to validate the extracted thermal resistance </i><i>values for two-layer material systems with an bonded interface, as well as for the </i><i>thermal conductivity measurement of bulk materials without an interface. The data extraction </i><i>process is shown to accurately extract thermal contact resistances on the order of </i><i>0.0001 cm</i><i>2</i><i>K/W in silicon-based packages for interfaces that are a few millimeters from the </i><i>exposed surface. For bulk materials, this technique demonstrates accuracy in extracting </i><i>the thermal conductivity of a wide range of materials ranging from thermal insulators to </i><i>highly conductive materials, spanning a range of 0.1 to 2000 W m</i><i>−1 </i><i>K</i><i>−1</i><i>. Physical measurements </i><i>of thermal conductivity of bulk silicon nitride and zinc oxide agree well with expected </i><i>reference values, and these measurements also align well with data from independently performed </i><i>experiments on the same materials using an established ASTM D5470 standard, </i><i>thereby validating this new measurement technique experimentally. Two-layer dry-contact </i><i>stacks of these two materials demonstrate the extraction of the thermal resistance across </i><i>interfaces buried up to 2 mm from the exposed surface. This work contributes toward standardization </i><i>of this technique for measurement of thermal resistances with low magnitudes </i><i>and buried depths, which are commonly found in modern electronic packages, ranging from </i><i>near-junction epitaxial semiconductor films to interconnect layers in emerging die-to-die and </i><i>wafer hybrid bonding technologies.</i></p><p dir="ltr"><i>Ultimately, these measurement techniques of in-plane thermal conductivity measurement </i><i>of anisotropic materials and the interfacial contact resistance measurements across buried </i><i>interfaces offer an important contribution to the area of thermal metrology, and advance the </i><i>field of next-generation semiconductor packaging.</i></p>

<p dir="ltr">The adoption of Heterogeneous Integration (HI) technologies in semiconductor packaging to build 2.5D/3D structures has led to increased power densities and material heterogeneity. These structures place a new burden on thermal and mechanical design. Additionally, these structures allow for significantly increased physical design freedom. With more possible layout options as well as tougher thermal constraints, new specialized tools are required to accelerate this type of design.</p><p dir="ltr">To address this problem using traditional finite element analysis Stack3D is presented. Stack3D is a steady-state thermal-mechanical geometry modeling and analysis platform for advanced packaging early design exploration. It is a finite element simulator developed from scratch in Matlab complete with symbolic geometry representation, automatic meshing, chip power map support, and sparse matrix acceleration.</p><p dir="ltr">After the development of Stack3D, methods for further accelerating the simulation process at the cost of solution accuracy were examined. Neural networks were selected as an engine for this task based on their millisecond evaluation time. In order to choose between the training paradigms of Physics Informed and Data Driven neural networks, a series of benchmarks were run to identify Data Driven networks as ideal candidates for steady state heat conduction.</p><p dir="ltr">Last, the first neural network model for fully generalized steady state heat conduction of 3D packages is developed. This is made possible by using the solution to the partial differential equation governing steady state heat conduction and casting the problem into an image-to-image translation framework. After accounting for the third spatial dimension, this allows the use of cutting edge image processing network for the heat conduction problem. After training, the network was able to run tens of thousands of simulations with an average of 0.53\% error and 0.0035 seconds per simulation.</p>