Power electronics is a constantly growing and demanding technical field. Consumer demand and developing technologies have made the improvement of power density a primary emphasis of research for this area. Power semiconductors present some of the major challenges for increasing system level power density due to high loss density and interconnection requirements. Advanced cooling schemes, such as double-sided, forced liquid convection or multi-phase flow, can be implemented with non-wire bond packaging to improve thermal management while maintaining proper electrical performance. Embedded power is one such packaging technology, which provides a compact structure for interface of power semiconductor to fluid flow. The objective of this work was to identify the potential of implementing embedded power packaging with double-sided forced liquid convection. Physics based, electro-thermal models were first used to predict the improvement in heat transfer of double-sided, forced liquid convection with embedded power packaging over single-sided liquid cooled wire bond based packaging. A liquid module test bed was designed and constructed based on the electro-thermal models, which could be interfaced with high power MOSFET based samples implementing various packaging technologies. Experiments were used to verify the model predictions and identify practical limitations of high flow rate, double-sided liquid cooling with embedded power. An improvement of 45% to 60% in total junction to case thermal resistance is shown for embedded power packaging with double-sided liquid cooling for water flow rates between 0.25 and 4.5 gal/min. / Master of Science

Abstract This thesis is mainly aimed to the study the basic physical properties of different flux, and the combination with semiconductor packaging of 0.6mm Sn96.5/Ag3.0/Cu0.5 (SAC305) big solder ball, and 0.3mm Sn98.5/Ag1.0/Cu0.5 (SAC105) small solder ball. Big solder ball was proceeded with shear stress test, pull ball test, and tray drop test. However small solder ball was proceeded with shear stress test, pull ball test, zone shear solder balls test and board level drop test. After experiments, samples of different flux, the effect of solder strength and mechanical properties were received and discussed. And failure modes were observed by high-power microscope, SEM and OM. The experimental result shows that the flux doesn¡¦t have direct relationship with the point of welding strong and weak, the point of welding strong and weak is determined by the metal¡¦s characteristics. However, the less of residual flux is, the higher the solder balls shearing force as well as pulling force are. As for the more of residual more of flux, after aged processing, some solder balls have the phenomenon of missing from the IMC layer. And the difference of the residual flux will affect the various failure modes of zone shear solder balls. From board level drop test, the majority of failure modes is pad peeling at the corner of test board side for all test flux, and the remaining failure modes exhibit solder fractured and IMC layer broken. Therefore, the judgement of the residual flux is a very important key factor for the semiconductor packaging. It doesn¡¦t have the direct correlation with the reliability of final products. Keywords: Lead Free, Solder Ball, Flux, Semiconductor Packaging, Tests.

Submitted by JOSIANE SANTOS DE OLIVEIRA (josianeso) on 2018-10-01T11:47:12Z No. of bitstreams: 1 Márcio Rafael Stracke_.pdf: 1667083 bytes, checksum: 7f8c37d9c5a822527980feaaec50278e (MD5) / Made available in DSpace on 2018-10-01T11:47:13Z (GMT). No. of bitstreams: 1 Márcio Rafael Stracke_.pdf: 1667083 bytes, checksum: 7f8c37d9c5a822527980feaaec50278e (MD5) Previous issue date: 2018-06-06 / HT Micron / Com o avanço da microeletrônica, cada vez mais surgem dispositivos eletrônicos portáteis. Isso traz diversos desafios à cadeia de semicondutores, desde o projeto, no desenvolvimento de circuitos integrados menores e mais eficientes até o encapsulamento, uma vez que os componentes tem ficado menores, mais finos e com um número maior de pinos de entrada e saída. Esses desafios estão presentes em todos os processos de fabricação de um chip e podemos citar a moldagem como um processo crítico em especial. A tecnologia de moldagem por transferência, que está consolidada e é a principal utilizada neste processo, necessita de cuidados especiais na otimização de seus parâmetros e materiais, tendo em vista os fatores citados e a consequente redução do diâmetro dos fios que realizam a interconexão do die com o substrato. Neste cenário, o wire sweep, que é o arraste destes fios de solda devido ao escoamento do encapsulante, acaba se tornando um problema, já que perdas no processo de moldagem implicam em sucatear o componente. A taxa de falhas devido a este tipo de falha podem chegar a 2,5%, segundo estudos de grandes fabricantes da cadeia de semicondutores divulgado em (SANDGREN; ROTH, 2004). Neste trabalho foi simulado o processo de moldagem de memórias DRAM com encapsulament do tipo BOC BGA, utilizando o módulo de FSI do software COMSOL. Os resultados da razão de wire sweep obtidos na simulação ficaram dentro do intervalo da média com um desvio padrão, na comparação com os valores reais medidos em peças fabricadas na condição simulada, tendo como erro máximo 15,26%. / The advancement of microelectronics makes more and more portable electronic devices emerge in our daily lives. This brings a number of challenges to the semiconductor chain, from design, to the development of smaller and more efficient integrated circuits to encapsulation, since the components have become smaller, thinner, and with a larger number of input and output pins. These challenges are present in all chip fabrication processes and we can define molding as a critical process in particular. The transfer molding technology, which is consolidated and the main one used in this process, requires special care in the optimization of its parameters and materials, since there are more and shorter wires realizing the connection between the die and the substrate. The wire sweep, which is the entrainment of the wires due to the flow of the mold compound, becomes a problem, since losses in the molding process imply scrapping the component. The failure rate due to this type of failure can reach 2.5%, according to studies by major semiconductor chain manufacturers disclosed in (SANDGREN; ROTH, 2004). In this project the DRAM memory molding process with BOC BGA encapsulation type was simulated using the FSI module in COMSOL software. Results of wire sweep ratio obtained are within the average adding or subtracting one standard deviation and the maximum error rate ranging was 15.26% considering manufactured boards using the simulation parameters.

Wide bandgap (WBG) semiconductor devices are becoming increasing popular in power electronics applications. However, WBG semiconductor devices generate a substantial amount of conducted electromagnetic interference (EMI) compared to silicon (Si) devices due to their ability to operate at higher switching frequencies, higher operating voltages and faster slew rates. This thesis explores and analyzes EMI mitigation techniques that can be applied to a power module architecture at the packaging level. In this thesis, the EMI footprint of four different module architectures is measured experimentally. A time domain LTspice simulation model of the experimental test setup is then built. The common mode (CM) EMI emissions that escape the baseplate of the module into the converter is then examined through the simulation. The simulation is used to explore the CM noise footprint of eight additional module architectures that were found in literature. The EMI trends and the underlying mitigation principle for the twelve modules is explained by highlighting key differences in the architectures using common mode equivalent modelling and substitution and superposition theorem. The work aims to help future module designers by not only comparing the EMI performance of the majority of module architectures available in literature but by also providing an analysis methodology that can be used to understand the EMI behavior of any new module architecture that has not been discussed. Although silicon carbide (SiC) modules are used for this study, the results are applicable for any WBG device. / M.S. / As society moves towards the electric grid of the future, there have been increasing calls for high efficiency, high power density, and low electromagnetic interference (EMI) power electronic converters. EMI is a big problem when using wide-bandgap (WBG) devices as these devices can switch very quickly and handle higher voltages when compared to silicon devices. In this study, ways to reduce EMI in a WBG power module through twelve different types of packaging are explored. Four WBG power modules are designed and fabricated in the lab, whereas a simulation model was created to study the EMI behavior of the remaining eight power module. The EMI behavior of these modules is explained using common mode (CM) equivalent modeling and substitution and superposition theorem. This study is important because WBG devices are becoming more and more popular in power electronic applications. The author hopes the findings and analysis presented in this paper can help future module designers reduce the EMI footprint of modules they design.