Continuous-time sigma-delta modulators play an important role in the development of biomedical sensors. It is suitable for monitoring of basic human vital functions (i.e., heartbeat and respiration). However, the physiological signal is very weak and it belongs to low-frequency range, the observed signals are strongly inter¬fered by the intrinsic flicker noise form CMOS transistors, which will cause a certain degree of difficulty in the identification. This thesis describes the implementation of loop filter using a differential chopper-stabilized configuration to reduce the influence of flicker noise on sigma-delta modulator within the signal bandwidth. The noise analysis of this sigma-delta modulator is calculated by the time-domain noise simulation. This method can take the noise factors into account when analyzing the overall performance. The proposed sigma-delta modulator is fabricated using TSMC 0.35£gm 2P4M CMOS technology. The chip area is 1.403 x 1.4 mm2. With a sampling rate of 20.8 kHz, the modulator achieves 84.4 dB of the peak SNDR and ENOB is 13.7-bit within signal band¬width of 10Hz. It dissipates 3.46 mW under 3V supply voltage.

The instrumentation amplifier (IA) is one of the crucial blocks in an electrocardiogram recording system. It is the first block in the analog front-end chain that processes the ECG signal from the human body and thus it defines some of the most important specifications of the ECG system like the noise and common mode rejection ratio (CMRR). The extremely low ECG signal bandwidth also makes it difficult to achieve a fully integrated system. In this thesis, a fully integrated IA topology is presented that achieves low noise levels and low power dissipation. The chopper stabilized technique is implemented together with an AC coupled amplifier to reduce the effect of flicker noise while eliminating the effect of the differential electrode offset (DEO). An ultra low power operational transconductance amplifier (OTA) is the only active power consuming block in the IA and so an overall low power consumption is achieved. A new implementation of a large resistor using the T-network is presented which makes it easy to achieve a fully integrated solution. The proposed IA operates on a 2V supply and consumes a total current of 1.4µA while achieving an integrated noise of 1.2µVrms within the bandwidth. The proposed IA will relax the power and noise requirements of the analog-to-digital converter (ADC) that immediately follows it in the signal chain and thus reduce the cost and increase the lifetime of the recording device. The proposed IA has been implemented in the ONSEMI 0.5µm CMOS technology.