The design of mineral processing circuits is a complex, open-ended process.  While several tools and methodologies are available, extensive data collection accompanied with trial-and-error simulation are often the predominant technical measures utilized throughout the process.  Unfortunately, this approach often produces sub-optimal solutions, while squandering time and financial resources.  This work proposes several new and refined methodologies intended to assist during all stages of circuit design.  First, an algorithm has been developed to automatically determine circuit analytical solutions from a user-defined circuit configuration.  This analytical solution may then be used to rank circuits by traditional derivative-based linear circuit analysis or one of several newly proposed objective functions, including a yield indicator (the yield score) or a value-based indicator (the moment of inertia). Second, this work presents a four-reactor flotation model which considers both process kinetics and machine carrying capacity.  The simulator is suitable for scaling laboratory data to predict full-scale performance.  By first using circuit analysis to reduce the number of design alternatives, experimental and simulation efforts may be focused to those configurations which have the best likelihood of enhanced performance while meeting secondary process objectives.  Finally, this work verifies the circuit analysis methodology through a virtual experimental analysis of 17 circuit configurations.  A hypothetical electrostatic separator was implemented into a dynamic physics-based discrete element modeling environment.  The virtual experiment was used to quantify the selectivity of each circuit configuration, and the final results validate the initial circuit analysis projections. / Ph. D.

The scrap metal recycling industry is a growing industry that plays an important role in the sustainability of a large global metal supply. Unfortunately, recycling lacks many standards, and test procedures in place for mineral processing. These standards and practices, if used in recycling, could aid recyclers in determining and achieving optimal separations for their plant.. New regulations for scrap imports into China make it difficult to obtain the metal recoveries that have been achieved in the past. In order to help scrap yards adhere to the new regulations the Eriez RCS eddy current separator system was tested in full scale. The principles this system uses, called circuit analysis, have been used by the mining industry for years, and can be used with any separation system. The Eriez RCS system surpassed the requirements of the Chinese regulations, while simultaneously increasing the recovery of metals. In order to further analyze eddy current separator circuits, tree analysis was attempted for single eddy current separators, as well as more complex circuits mimicked using locked cycle tests. The circuits used in the locked cycle test were a rougher-cleaner, a rougher-scavenger, and a rougher-cleaner-scavenger. It was found that it is possible to use tree analysis to compare different eddy current separator circuits using the same settings, however standards for this practice need to be established for it to be useful. Using the data analysis methods developed for this particular tree analysis, the rougher-cleaner-scavenger test had the best performance overall. This is the same result as the full scale testing done on the Eriez RCS system, but more testing should be conducted to confirm the data analysis techniques of calculating theoretical efficiency, recovery efficiency, and rejection efficiency. / Master of Science

No description available.

Chip temperature is increasing with continued technology scaling due to increased power density and decreased device feature sizes. Since temperature has significant impact on performance and reliability, accurate thermal and circuit analysis are of great importance. Due to the shrinking device feature size, effects occurring at the nanometre scale, such as ballistic transport of energy carriers and electron tunneling, have become increasingly important and must be considered. However, many existing thermal and circuit analysis methods are not able to consider these effects efficiently, if at all. This thesis presents methods for accurate and efficient multi-scale thermal and circuit analysis. For circuit analysis, the simulation of single-electron device circuits is specifically studied. To target thermal analysis, in this work, ThermalScope, a multi-scale thermal analysis method for nanometre-scale IC design is developed. It unifies microscopic and macroscopic thermal physics modeling methods, i.e., the Boltzmann transport and Fourier modeling methods. Moreover, it supports adaptive multi-resolution modeling. Together, these ideas enable efficient and accurate characterization of nanometre-scale heat transport as well as chip-package level heat flow. ThermalScope is designed for full chip thermal analysis of billion-transistor nanometre-scale IC designs, with accuracy at the scale of individual devices. ThermalScope has been implemented in software and used for full chip thermal analysis and temperature-dependent leakage analysis of an IC design with more than 150 million transistors. To target circuit analysis, in this work, SEMSIM, a multi-scale single-electron device simulator is developed with an adaptive simulation technique based on the Monte Carlo method. This technique significantly improves the time efficiency while maintaining accuracy for single-electron device and circuit simulation. It is shown that it is possible to reduce simulation time up to nearly 40 times and maintain an average propagation delay error of under 5% compared to a non-adaptive Monte Carlo method. This simulator has been used to handle large circuit benchmarks with more than 6000 junctions, showing efficiency comparable to SPICE, with much better accuracy. In addition, the simulator can characterize important secondary effects including cotunneling and Cooper pair tunneling, which are critical for device research. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2008-09-26 13:33:12.389

Thesis (Ph. D.)--Ohio University, August, 2003. / Title from PDF t.p. Includes bibliographical references (leaves 100-109).

Thesis (M. App. Sc.)--Carleton University, 2002. / Includes bibliographical references (p. 85-89). Also available in electronic format on the Internet.

Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1993. / Vita. Abstract. Includes bibliographical references (leaves 38-39). Also available via the Internet.

For many years some people have dismissed the idea that small generators placed close to loads could replace large central generation plants. In the near future, this idea will probably hold true. However, many companies today are producing small generators that will have a great impact on the power grid. These generators can be used to improve the overall service to a particular area. Also, these generators can also be used to save an electric utility or end-use customer a significant amount of money. However, there are a lot of concerns in using distributed generation. As a result, there are many different issues that need to be investigated when distributed generation is used. In this thesis, a guidebook is developed for an engineer to use when distributed generation is being considered. By following this guidebook an engineer should be able to investigate proper engineering and economic issues. The engineering issues the engineer should consider are coordination, application of protective devices, voltage control, transformer winding configuration, reduction of losses and islanding. By following this guidebook, the engineer should also consider certain economic issues that include the impact of distributed generation on generation, transmission and distribution companies, the impact of distributed generation on wholesale and retail rates, and the costs associated with installation, operation and maintenance of distributed generation. As an example application, the requirements found in the guidebook are applied to a particular scenario for an existing facility that is served by a distribution company.

An algorithm is derived for the removal of the DC offset from a faulted current signal using a microprocessor sampling on real-time. The algorithm is to be used instead of the analog Mimic circuit in distance computer relaying. Four variations of the algorithm were derived and tested to determine the best compromise between time response and noise sensitivity. The relay hardware is taken into consideration for the derivations to avoid adding any hardware to the relay. The graphical results of the test run in an analog simulator at the Virginia Tech Power Systems Laboratory are presented. Faults at different voltage angles were performed to determine the algorithm's performance at different levels of DC offset. From the graphical response obtained from the test and taking into consideration hardware and software limitations, a preferred algorithm is selected with a good compromise between time response and noise sensitivity. / Master of Science

Guided probe testing of printed circuit boards is a technique that has been well developed by automatic test equipment manufacturers to pinpoint faults. Though the guided probe technique of testing printed circuit boards is a process capable of providing high diagnostic resolution, the technique is inefficient when it is performed manually. The throughput of board testing is bottlenecked because of the time required for an operator to manually move a probe to a specific location on the board under test in order to measure a stimulated response. Integration of a CAD driven X-Y prober is a way to automate guided probe testing of printed circuit boards. This research integrates a personal computer based automated guided probe testing system. A CAD tool provides geometric and circuit connectivity information. Automatic test generation, CAD information post processing, and automatic guided probe testing software tools are developed to implement the system. The ultimate result is increased circuit board test station throughput. This makes the circuit board manufacturing process more efficient and less expensive while maintaining high quality products through more extensive testing. / Master of Science