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DESIGN OF CLASS F-BASED DOHERTY POWER AMPLIFIER FOR S-BAND APPLICATIONSChang, Kyle 01 June 2023 (has links) (PDF)
Modern RF and millimeter-wave communication links call for high-efficiency front end systems with high output power and high linearity to meet minimum transmission requirements. Advanced modulation techniques, such as orthogonal frequency-division multiplexing (OFDM) require a large power amplifier (PA) dynamic range due to the high peak-to-average power ratio (PAPR). This thesis provides the analysis, design, and experimental verification of a high-efficiency, high-linearity S-band Doherty power amplifier (DPA) based on the Class F PA. Traditional Class F PAs use harmonically tuned output matching networks to obtain up to 88.4% power-added efficiency (PAE) theoretically, however the amplifier experiences poor linearity performance due to switched mode operation, typically yielding less than 30dB C/I ratio [1]. The DPA overcomes this linearity limitation by using an auxiliary amplifier to boost output power when the amplifier is subject to a high input power due to its limited conduction cycle. The DPA also provides improved saturated output power back-off performance to maintain high PAE during operation.
The DPA presented in this thesis optimizes PAE while maintaining linearity by employing harmonically tuned Class F amplifier topology on a primary and an auxiliary amplifier. A Class F PA is first designed and fabricated to optimize output network linearity – this is followed by a DPA design based on the fabricated Class F PA. A GaN HEMT Class F PA and DPA operating at 2.2GHz are implemented with the PAs measuring 40% and 45% PAE respectively while maintaining a 30dB carrier-to-intermodulation (C/I) ratio on a two-tone test. The PAE is characterized at maximum 21dBm input power per tone and 20MHz tone spacing. When subject to a single 24dBm continuous wave input tone, the Class F PA and DPA output 37dBm and 35.5dBm respectively. The PAs presented in the thesis provide over 30dB C/I ratio up to 21dBm input tones while maintaining over 40% PAE suitable for base station applications.
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Oscillateur de puissance en ondes millimétriquesDréan, Sophie 19 December 2012 (has links)
Ce travail porte sur l'étude d'un oscillateur de puissance contrôlé en tension en ondes millimétriques. L'objectif de la thèse est de concevoir cet oscillateur pour la bande de fréquence utilisée dans les standards IEEE 802.15.3c, IEEE 802.11ad et ECMA TC48, à savoir 56GHz-65GHz. Le principe de l'oscillateur de puissance est développé autour d'un amplificateur de puissance rebouclé pour engendrer un système oscillant. L'amplificateur de puissance développé est un amplicateur à deux étages. Celui de puissance est de classe E et le driver est de classe F. La boucle de retour est basée sur un vecteur-modulateur. Les circuits ont été fabriqués en technologie CMOS 65nm de STMicroelectronics. / This PhD thesis deals with a Power Voltage Controlled Oscillator (VCO) in millimeter waves. The aim is to design this Power VCO in the frequency band used in the standards IEEE 802.15.3c, IEEE 802.11ad and ECMA TC48, meaning from 56GHz to 65GHz. The principle of this oscillator is developed around a power amplifier in a loop, generating an oscillating system. The power amplifier is developed in a two-stage topology. The power stage is composed with a 60GHz class E cascoded amplifier and the driver stage is composed of a 60GHz class F amplifier. The feedback of the loop is based on a vector-modulator. The circuits have been realised in 65nm CMOS technology from STMicroelectronics.
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Design methods for integrated switching-mode power amplifiersBozanic, Mladen 24 July 2011 (has links)
While a lot of time and resources have been placed into transceiver design, due to the pace of a conventional engineering design process, the design of a power amplifier is often completed using scattered resources; and not always in a methodological manner, and frequently even by an iterative trial and error process. In this thesis, a research question is posed which enables for the investigation of the possibility of streamlining the design flow for power amplifiers. After thorough theoretical investigation of existing power amplifier design methods and modelling, inductors inevitably used in power amplifier design were identified as a major drawback to efficient design, even when examples of inductors are packaged in design HIT-Kits. The main contribution of this research is engineering of an inductor design process, which in-effect contributes towards enhancing conventional power amplifiers. This inductance search algorithm finds the highest quality factor configuration of a single-layer square spiral inductor within certain tolerance using formulae for inductance and inductor parasitics of traditional single-π inductor model. Further contribution of this research is a set of algorithms for the complete design of switch-mode (Class-E and Class-F) power amplifiers and their output matching networks. These algorithms make use of classic deterministic design equations so that values of parasitic components can be calculated given input parameters, including required output power, centre frequency, supply voltage, and choice of class of operation. The hypothesis was satisfied for SiGe BiCMOS S35 process from Austriamicrosystems (AMS). Several metal-3 and thick-metal inductors were designed using the abovementioned algorithm and compared with experimental results provided by AMS. Correspondence was established between designed, experimental and EM simulation results, enabling qualification of inductors other than those with experimental results available from AMS by means of EM simulations with average relative errors of 3.7% for inductors and 21% for the Q factor at its peak frequency. For a wide range of inductors, Q-factors of 10 and more were readily experienced. Furthermore, simulations were performed for number of Class-E and Class-F amplifier configurations with HBTs with ft greater than 60 GHz and total emitter area of 96 μm² as driving transistors to complete the hypothesis testing. For the complete PA system design (including inductors), simulations showed that switch-mode power amplifiers for 50 Ω load at 2.4 GHz centre frequency can be designed using the streamlined method of this research for the output power of about 6 dB less than aimed. This power loss was expected, since it can be attributed to non-ideal properties of the driving transistor and Q-factor limitations of the integrated inductors, assumptions which the computations of the routine were based on. Although these results were obtained for a single micro-process, it was further speculated that outcome of this research has a general contribution, since streamlined method can be used with a much wider range of CMOS and BiCMOS processes, when low-gigahertz operating power amplifiers are needed. This theory was confirmed by means of simulation and fabrication in 180 nm BiCMOS process from IBM, results of which were also presented. The work presented here, was combined with algorithms for SPICE netlist extraction and the spiral inductor layout extraction (CIF and GDSII formats). This secondary research outcome further contributed to the completeness of the design flow. All the above features showed that the routine developed here is substantially better than cut-and-try methods for design of power amplifiers found in the existing body of knowledge. / Thesis (PhD(Eng))--University of Pretoria, 2011. / Electrical, Electronic and Computer Engineering / unrestricted
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