In many systems today sensors or transmitters need to be read or controlled simultaneously. This thesis investigates a new architecture used for deskewing clock signals between multiple separated parts of a signal transmission system. The original application is a multi-channel MEMS transceiver system utilizing beamforming, split into two separate modules. The presented architecture has been developed after evaluating multiple alternative systems. Special focus has been on the locking time of the full system. Furthermore, the scalability for use in implementations with requirements for interconnection delays, as well as input frequency and final timing skew. The full system consists of two parts, a master- and a slave-system. A proof-of-concept transistor implementation has been done in a 180 nm CMOS process. It has been simulated to verify the functionality with varying interconnection delays, i.e., wire lengths up to 1 m. The results from the simulations show that the system works as intended with a skew less than the required 1 ns for a 10 MHz clock signal. This fulfills the requirement for the original application. Further work is required to finalize the presented system before deployment in an actual product