This thesis aims at investigating size dependence of properties of nanostructures from the point of view of a general scaling theory that smoothly connects properties of the bulk to that of nanostructures. Two different examples of a ``static'' and a ``dynamic'' property are considered in this study. The first example studied is of size dependence of coefficient of thermal expansion (CTE) which a static property of nanostructures. The CTE of nanobars and nanoslabs is studied using equilibrium molecular dynamics and dynamical matrix formulation in an electrically insulating medium. It is found that the fractional change in CTE from the bulk value scales inversely with the size of the nanostructures, thus, showing a simple description in terms of a scaling theory. In the second part, electron transport in carbon nanotube field effect transistors (CNTFETs) is studied using Landauer formalism. A CNTFET involves transport through a 1-d ballistic carbon nanotube channel with Schottky barriers (SB) at contacts which determines the transport characteristics. The CNT is modeled as a 1-d semiconductor having only two bands separated by an energy gap which depends inversely on tube diameter. After the contact is made, a self-consistent potential appears due to charge transfer between CNT and metal, which is calculated by solving Poisson equation. The electron transmission across the barriers is calculated using WKB approximation. Current and conductance are calculated using Landauer-Buttiker formula. Diameter dependence of properties like, conductance, threshold voltage, VON, etc. is calculated. It is found that there is no simple scaling for a property for small values of diameter. The scaling form is, however, found to be valid for larger diameters. Also, other calculated device characteristics are in close agreement with experiments. The model presented in this thesis is the first detailed study illustrating the applicability of the scaling approach to the properties of nanostructures. The static properties show scaling behavior, while ``dynamic'' properties derived from electronic response do not.

International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California / Eutectic (63% tin-37% lead) or near-eutectic (40% tin-60% lead) tin-lead solder is widely used for creating electrical interconnections between the printed wiring board (PWB) and the components mounted on the board surface. For components mounted directly on the PWB mounting pads, that is, surface mounted components, the tin-lead solder also constitutes the mechanical interconnection. Eutectic solder has a melting point of 183°C (361°F). It is important to realize that its homologous temperature, defined as the temperature in degrees Kelvin over its melting point temperature (T(m)), also in degrees Kelvin, is defined as T/T(m). At room temperature (25°C = 298K), eutectic solder's homologous temperature is 0.65. It is widely acknowledged that materials having a homologous temperature ≥ 0.5 are readily subject to creep, and the solder joints of printed wiring assemblies are routinely exposed to temperatures above room temperature. Hence, solder joints tend to be subject to both thermal fatigue and creep. This can lead to premature failures during service conditions. The geometry, that is, the lead configuration, of the joints can also affect failure. Various geometries are better suited to withstand failure than others. The purpose of this paper is to explore solder joint failures of dual in-line (DIP) integrated circuit components, leadless ceramic chip carriers (LCCCs), and gull wing and J-lead surface mount components mounted on PWBs.