Although the field of Teaching Chinese as a Foreign Language (TCFL) is still a relatively emerging one, its history runs much longer than we expect. As early as the mid to late 19th Century, Chinese was being shown in way that had not been done before – as textbooks. More importantly, these textbooks were created by non-native speakers. Yet their value as historical documents and as foundation pedagogical resources has not yet been fully recognized. The present study is an initial conversation of four late 19th century textbooks and how they pioneered presenting Chinese to a Western audience. After discussing the theoretical differences between China and the West that led to the need for textbooks, the four textbooks will be compared on how they addressed the aspects of pronunciation, tones, characters and the skills of reading, writing and speaking to their respective audiences. Such comparisons should reveal that by understanding the learner’s perspective and utilizing non-native knowledge, these textbook authors were able to teach Chinese as a pedagogically progressive, learnable language. This study should not only add depth to our knowledge of the historical foundations and teaching precedents, but will also highlight the ways Chinese was instructed and how this can positively impact our modern teaching.

Reducing circuit complexity to minimize design turnaround time and maximize chip area utilization is the most evident problem in dealing with VLSI layout. Three suggestions have been recommended to reduce circuit complexity. They are using regular modules as design targets, using hierarchical top-down design as a design methodology, and using CAD as a design tool. These three suggestions are the basis of this dissertation project. In this dissertation, three silicon compilers were implemented which take an universal AHPL circuit description as an input and automatically translate it into SLA (Storage Logic Array), PPLA (Path Programmable Logic Array), and ULA (Uncommitted Logic Array) chip layout. The goal is to study different layout algorithms and to derive better algorithms for alternative VLSI structures. In order to make a precise chip area comparison of these three silicon compilers, real SLA and ULA circuits have been designed. Four typical AHPL descriptions of different circuits or varying complexity were chosen as comparison examples. The result shows that the SLA layout requires least area for circuit realization generally. The PPLA approach is the worst one for large scale circuit realization, while the ULA lies in between.

The subject of this investigation is a specific set of parsers known as LR parsers. Of primary interest is a LR parsing method developed by DeRemer which specifies a translation method which can be defined by a Deterministic Push-Down Automation (DPDA). The method of investigation was to apply DeRemer's parsing technique to a specific language known as THIS Programming Language (TPL). The syntax of TPL was redefined as state diagrams and these state diagrams were, in turn, encoded into two tables--a State-Action table and a Transition table. The tables were then incorporated into a PL/l adaptation of DeRemer's algorithm and tested against various TPL statements.

Typescript (photocopy). / Digitized by Kansas Correctional Industries / Department: Computer Science.

Typescript (photocopy). / Digitized by Kansas Correctional Industries / Department: Computer Science.

Typescript (photocopy). / Digitized by Kansas Correctional Industries

The subject of this thesis is the design of a FORTRAN compiler for the PDP-11/34 minicomputer owned by the Dept. of Mathematical Sciences of Ball State University, Muncie, Indiana. At the time that this project was undertaken, only the BASIC and ASSEMBLY languages were available on this machine.The problem consisted of writing a two-pass processer. The function of the first pass was to recognize FORTRAN statements, analyze them syntactically and semantically, build symbol tables, and construct an output file containing pointers to the symbol table, flags, and operators. The second pass used the output file of the first part and the symbol tables to build ASSEMBLY language instructions equivalent to the FORTRAN instructions in function.Ball State UniversityMuncie, IN 47306

Thesis (M.S.)--Mississippi State University. Department of Computational Engineering. / Title from title screen. Includes bibliographical references.

Thesis (Ph. D.)--University of Missouri-Columbia, 2002. / Typescript. Vita. Includes bibliographical references (leaves 134-137). Also available on the Internet.

Thesis (Ph. D.)--University of Missouri-Columbia, 2002. / Typescript. Vita. Includes bibliographical references (leaves 134-137). Also available on the Internet.