Global ETD Search

311	Pipelined Design Approach To Microprocessor Architectures A Partial Implementation: Mips Altinigneli, Muzaffer Can 01 December 2005 (has links) (PDF) This thesis demonstrate how pipelining in a RISC processor is achieved by implementing a subset of MIPS R2000 instructions on FPGA. Pipelining, which is one of the primary concepts to speed up a microprocessor is emphasized throughout this thesis. Pipelining is fundamentally invisible for high level programming language user and this work reveals the internals of microprocessor pipelining and the potential problems encountered while implementing pipelining. The comparative and quantitative flow of this thesis allows to understand why pipelining is preferred instead of other possible implementation schemes. The methodology for programmable logic development and the capabilities of programmable logic devices are also given as background information. This thesis can be the starting point and reference for programmers who are willing to get familiar with microprocessors and pipelining. Microprocessor, MIPS, Pipelining, FPGA
312	Compact modeling of SiGe HBTs using VERILOG-A Feng, Zhiming Niu, Guofu. January 2006 (has links) (PDF) Thesis(M.S.)--Auburn University, 2006. / Abstract. Vita. Includes bibliographic references.
313	Hardware implementation of a synchronization state buffer in VHDL Barton, Jonathan L. January 2008 (has links) Thesis (M.E.E.)--University of Delaware, 2008. / Principal faculty advisor: Guang R. Gao, Dept. of Electrical and Computer Engineering. Includes bibliographical references.
314	An artificial neural network with reconfigurable interconnection network Leija, Carlos Ivan, January 2008 (has links) Thesis (M.S.)--University of Texas at El Paso, 2008. / Title from title screen. Vita. CD-ROM. Includes bibliographical references. Also available online.
315	Design and simulation of a primitive RISC architecture using VHDL / Moustakas, Evangelos. January 1991 (has links) Thesis (M.S.)--Rochester Institute of Technology, 1991. / Spine title: Design of a RISC using VHDL. Typescript. Includes bibliographical references (leaf 71).
316	Simulation of a morphological image processor using VHDL. mathematical components / Chen, Wei-chun. January 1993 (has links) Thesis (M.S.)--Rochester Institute of Technology, 1993. / Typescript. Includes bibliographical references (leaf 96).
317	Simulation of a morphological image processor using VHDL. control mechanism / Chen, Hao. January 1993 (has links) Thesis (M.S.)--Rochester Institute of Technology, 1993. / Typescript. Includes bibliographical references (leaf 101).
318	An evaluation of CoWare Inc.'s Processor Designer tool suite for the design of embedded processors Franz, Jonathan D. Duren, Russell Walker. January 2008 (has links) Thesis (M.S.E.C.E.)--Baylor University, 2008. / Includes bibliographical references (p. 322-323)
319	Timing distribution in VHDL behavioral models / Gadagkar, Ashish, January 1992 (has links) Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1992. / Vita. Abstract. Includes bibliographical references (leaves 97-100). Also available via the Internet.
320	Architecture exploration for embedded processors with LISA / Hoffmann, Andreas. Leupers, Rainer. Meyr, Heinrich. January 2002 (has links) Techn. Hochsch., Diss. u.d.T.: Hoffmann, Andreas: A methodology for the efficient design of application-specific instruction-set processors using the machine description language LISA--Aachen, 2002.

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