In this thesis, the efficient simulation of large-scale system-level VHDL models is analyzed. The system-level models chosen for the investigation are multicomputer networks, which are scalable up to thousands of processing nodes. Initially, a classification of parallel processing architectures is presented along with performance criteria and design issues related to the various interconnection network topologies. Communication and synchronization issues of MIMD systems are explored. A major limitation of planar tree structures is discussed along with a solution to help alleviate the problem, which is to make use of the binary fat-tree. Practical aspects of efficiently simulating large behavioral and structural models (using the fat-tree model as a case study), on a uniprocessor system are analyzed. The system resources of the workstation used to perform the simulations are carefully monitored to see where resource utilization problems usually occur. The size of the model is increased and the run time of the simulation compared with that of smaller sized models. A memory threshold level is detected after which memory resource contention problems occur and the simulation efficiency declines. One of the problems observed in simulating complex models is the fact that simulation runs take a very long time to execute. A multicomputer using the fat-tree interconnection network is proposed as a suitable architecture for the distributed simulation of VHDL models. Various algorithms used for the parallel discrete event simulation (PDES) of VHDL models are evaluated. The feasibility of this approach is evaluated by analyzing the factors affecting the performance of the proposed architecture. The number of hops a message takes to travel from one processor to another in the fat-tree is used to estimate the time of an event message between two processors. The roll-back and communication costs amongst the processing nodes are taken into consideration when evaluating the speedup of the simulation time of a VHDL model, simulated over multiple processors. The speedup of the simulation obtained by using the fat-tree topology is compared with the results obtained with a linear array of processors. The future inclusion of the "shared variable" into the language and its impact on the implementation of parallel simulators on multicomputer networks is analyzed. / Master of Science

This thesis describes a Natural Language (NL) interface to a VHDL modeling tool called the Modeler's Assistant. The primary motivation for the interface developed in this research work is to permit VLSI modelers who are not proficient in VHDL to rapidly produce correct VHDL models from manufacturer's descriptions. This tool should also be useful in teaching the VHDL language. The Modeler's Assistant has supported graphical capture of behavioral models in the form of Process Model Graphs consisting of processes (nodes) interconnected by signals (arcs). The NL interface that has been constructed allows modelers to specify the behavior for the process nodes using a restricted form of English called ModelSpeak. A Spell-checking routine (of the UNIX operating system) is invoked to reduce input errors. Also, the grammar employed, accepts multi-sentence descriptions rather than just a single sentence. Correct VHDL for each process is synthesized automatically, but user interaction is solicited where needed to resolve ambiguities such as the scope of loops and the type of signals and variables. The Modeler's Assistant can then assemble the VHDL code for these processes, along with the information about the interface description from the PMG, into a complete entity model. / Master of Science

This paper presents an approach for representing and simulating High Level Languages (HLL) using VHDL behavioral models. The graphical representation, a Data Flow Graph (DFG), is used as a base for the VHDL representation and simulation of a High Level Language (C). A package of behavioral models for the functional units for the High Level Language as well as individual entities has been developed using VHDL. An algorithm, Graph2VHDL, accepts a Data Flow Graph representation of a High Level Language and constructs a VHDL model for that graph. The representation of a High Level Language in VHDL frees users of custom computing platforms from the tedious job of developing a hardware model for a desired application. The algorithm also constructs a test file that is used with a pre-existing program, Test Bench Generation (TBG), to create a test-bench for the VHDL model of a Data Flow Graph. The test bench that is generated is used to simulate the representation of the High Level Language in the Data Flow Graph format. Experimental results verify the representation of the High Level Language in the Data Flow Graph format and in VHDL is correct. / Master of Science

This thesis describes a new CAD tool, TIMESPEC, developed for solving the timing distribution problem of allocating realistic delays to the internal primitives of a digital device. The inconsistencies in the manufacturer's specifications are also detected and corrected. Therefore, TIMESPEC enables the use of imbedded timing in behavioral VHDL models, thereby providing accurate VHDL descriptions. Due to this modeling methodology, the end-to-end delays for all the paths in the digital device are made available. Also, due to the Register Transfer Level (RTL) of abstraction, which is represented by a process model graph, there is close correspondence with the actual device being modeled. Thus a better insight into the timing problems is provided and synthesis is possible from the resulting models. A linear programming approach is employed for solving the timing distribution problem. An interface is provided with an X-windows based graphical tool, the Modeler's Assistant. This provides a graphical interface for TIMESPEC. An important feature, that is made available by this interface, is the enumeration of all the input-to-output paths in the device. Thus a CAD tool is made available for system or chip designers/modelers for building accurate VHDL models where the timing is incorporated using the imbedded timing method. / Master of Science

Timing hazards are common problems found in logic circuits. A new integrated hazard detection system (HDS), which is implemented in VHDL, is proposed to detect the static, the dynamic, and the function hazards in any logic circuit that is described structurally in VHDL. This system adopts the IEEE VHDL Model Standard Group 1076-1164 Nine-Valued Multiple-Valued Logic package. Without any designer-supplied arbitrary input test patterns, the system predicts which input combinations will cause hazards, reports what type of hazards, and provides detailed timing information on the hazards in the combinational logic circuit with fixed gate delays. / Master of Science

This thesis describes two ongoing projects at Virginia Tech called ASPIN and the Modeler's Assistant, but is primarily concerned with a computer program known as "The VHDL Linker." This program is an interface between the two systems and interprets conceptual graphs generated from English sentences describing the behavior of a device, and produces a Process Model Graph and the associated VHDL code for use by the Modeler's Assistant. The ASPIN (Automated SPecification INterpreter) system translates English sentences describing the behavior of a device into a data structure known as conceptual graphs. Ultimately block diagrams and timing diagrams will be translated as well. The VHDL Linker translates these conceptual graphs into Process Model Graphs (PMGs) and corresponding VHDL code. Once a PMG (and associated VHDL code) has been created it can be edited as needed on the Modeler's Assistant, to fill in any holes left by the interpreters, correct errors, expand the model, or make it more specific as component designs become available. This research is the first step towards the development of a system which will allow a designer who is unfamiliar with VHDL to create a working VHDL model from informal specifications. Such a system will reduce the time from initial conception to a working design dramatically. / Master of Science

This thesis discusses an algorithm for mapping conceptual graphs to primitive VHDL processes. The behavior of each primitive process is stored in the form of a schema. The algorithm identifies concepts in the input referring to MODAS (Modeler's Assistant) process primitives and maps their schemata to the input conceptual graph. The results of the mapping are used to modify the primitive process's VHDL and instantiate a new process. A library of schemata for the primitive processes in MODAS has been developed. This algorithm has been implemented in the CGVHDL Linker program. It has improved the capability of the CGVHDL Linker to handle more complex design specifications. The algorithm provides the CGVHDL Linker with the ability to interpret a structure in the input conceptual graph. It also eases the burden on the designer who can refer to some components without giving details of their behavior. / Master of Science

This thesis describes the development of a graphical CAD tool for VHDL model development. The tool was developed for the X Windows environment. The graphical representation used is the process model graph [1,4]. The process model graph is input interactively and the tool generates the corresponding VHDL code. The design style is restricted to behavioral models. A new scheme was formulated for the development and use of reusable code in the form of primitives. A default set of primitives as presented in [5] was also developed. The tool can also attach to any VHDL analyzer available on the system and analyze the developed code. This tool is designed for use by system modelers and should simplify the process of model development, thus improving productivity. / Master of Science

Verification of a model describing a hardware system is very important for modeling and simulation purposes. It is necessary to ensure that the model accurately describes the hardware system. A scheme for the automatic verification of VHDL (VHSIC Hardware Description Language) models has been proposed. In the proposed scheme the specifications for the hardware system, i.e.,the timing constraints and relations between input and output signals are described by the designer in Modified Linear Time Temporal Logic,. which is an extension to traditional boolean logic and can describe timing relation between signals. A semantic similarity between temporal operators and VHDL timings and delays has been drawn and an algorithm for comparing the VHDL model and temporal specifications has been developed. Comparisons are made between the simulation results on the VHDL model and the temporal logic specifications and discrepancies are reported. / Master of Science

No description available.