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published_or_final_version / Computer Science and Information Systems / Master / Master of Philosophy

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With the advent of LSI and VLSI technology, the demand and affordability of custom tailored design has increased considerably. A short turnaround time is desirable along with more credible testing techniques. For a low-production device it is necessary to reduce the time and money spent in the design process. Traditional hardware design automation techniques rely on extensive engineer interaction. A detailed description of the circuit to be manufactured must be entered manually. It is often necessary to prepare a separate description for each phase of the design process. In order to be successful, a modern design automation system must be capable of supporting all phases of design activities from a single circuit description. It must also provide an adequate level of abstraction so that the circuit may be described conveniently and concisely. Such abstraction is provided by computer hardware description languages (CHDL). In this research, an automation system based on AHPL (A Hardware Programming Language) has been developed. The project may be divided into three distinct phases: (1) Upgrading of AHPL to make it more universally applicable; (2) Implementation of a compiler for the language; and (3) Illustration of how the compiler may be used to support several phases of design activities. Several new features have been added to AHPL. These include: application-dependent parameters, multiple clocks, asynchronous results, functional registers and primitive functions. The new language, called Universal AHPL, has been defined rigorously. The compiler design is modular. The parsing is done by an automatic parser generated from the SLR(1) BNF grammar of the language. The compiler produces two data bases from the AHPL description of a circuit. The first one is a tabular representation of the circuit, and the second one is a detailed interconnection linked list. The two data bases provide a means to interface the compiler to application-dependent CAD systems. In the end, a discussion on how the AHPL compiler can be interfaced to other CAD systems is given, followed by examples from current applications and from ongoing research projects. These applications illustrate the usefulness of a CHDL-based approach to the design of digital hardware automation systems.

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Manual design methods used successfully up to now for SSI and MSI parts are inadequate for logically complex and densely packed VLSI circuitry. Automating the design process has, therefore, become an essential goal of present-day practice. Hardware description languages form a useful front-end to the design-automation process which ultimately generates masks suitable for chip fabrication. AHPL has long been in use as a vehicle for the description of clock-mode digital systems. Supporting software packages include a simulator which allows the designer to debug his design at a functional level. A subsequent 3-stage compiler extracts global information contained in the original AHPL description to produce a comprehensive data-base. It then generates hardware specifications suitable for down-stream design and manufacturing activities. The SLA is an evolution of the PLA concept. Design with SLA's has the notable advantage of allowing hardware representation of functional and layout information, while sidestepping the costly and time-consuming placement and routing problem. This dissertation describes a methodology for translation to an SLA form of hardware realization from an AHPL description. The global information extracted from the AHPL data-base plays a prominent part in guiding the heuristic placement and routing algorithms.

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