No description available.

No description available.

No description available.

No description available.

No description available.

This thesis proposes a low-IF receiver architecture suitable for the realization of single-chip receivers. To alleviate the image-rejection requirements of the front-end filters an oversampling complex discrete-time ΔΣ ADC with a signal-transfer function that achieves a significant filtering of interfering signals is proposed. A filtering ADC reduces the complexity of the receiver by minimizing the requirements of analog filters in the IF digitization path. Discrete-time ΔΣ ADCs have precise resonant frequency and clock frequency ratios and, hence, do not require the calibration or tuning that is necessary in the case of continuous-time ΔΣ modulator implementations. This feature makes the proposed discrete- time ΔΣ ADC ideal for multistandard receiver applications.

No description available.

Approved for public release; distribution is unlimited. / As the navy transitions to all electric warships, there will be many changes to the power distribution schemes found aboard ships today. It will be necessary to maintain reliability while supplying the various components onboard with the proper voltage levels. Since transformers cannot be used to alter voltage levels while providing galvanic isolation in DC power systems, it is necessary to find an efficient method to incorporate the increased safety provided by galvanic isolation in a DC power distribution system. This thesis examines the design and control of one possible element for a future Electrical Distribution System (EDS), a DC-DC converter with galvanic isolation. The main purpose of this study is to provide a working model with associated theoretical proof and simulations. MATLAB will be used to provide observations of the converter's operation and the success of the control scheme implemented. Future work on this topic will be assisted by the inclusion of a parts list as well as recommendations for enhancing the prospects of this technology. / Ensign, United States Navy

The design of mixed-signal integrated circuits has evolved from simple analog and digital circuits operating on the same silicon substrate to the point that now we have complete system on a chip solutions for communication systems. The levels of integration needed to remain cost effective in today's integrated circuit (IC) market require careful use of all the available die space. The current trend of digital to analog converter (DAC) design has focused on maximizing speed and linearity for high performance telecommunications systems. The circuit design methods used to achieve very high sample rates require the use of large amounts of die space. This thesis presents a 10-bit DAC that has been optimized for area, while still maintaining accurate operation at low frequencies. To achieve 10-bit performance, an ultra high gain op-amp is introduced for various servoing applications in the DAC. The architecture chosen for the DAC will show an optimization of required die size and performance when compared to other architectures. The DAC was fabricated in a standard digital 0.18 μm CMOS process. The DAC occupies 0.0104 mm² (110 μm x 94 μm), and only consumes 2.8 mW of power. In addition to the 10-bit DAC, a design is presented for a 13-bit DAC which occupies 0.020 mm², and requires only the addition of a minimum number of devices to the 10-bit DAC. / Graduation date: 2002

Utilizing a two-capacitor topology, the digital implementation of an audio-band successive-approximation analog-to-digital converter (ADC) is explored in the context of mismatch-shaping where the mismatch estimates are accurate to the first order. A second-order ����� loop was found to be effective in system simulations given a 0.1% capacitor mismatch. Spectral analysis of the ADC shows dramatic improvements in total harmonic distortion as well as 87 dB SNDR (signal to noise and distortion ratio) for an oversampling ratio of 10. / Graduation date: 2002