This essay aims to illustrate how teachers from two different schools work to convey values in their professional roles, according to the basic values found in the Swedish curriculum Lgr11. This has been done through qualitative interviews with these schools’ teachers, individual at one school and in a group at the other. The results show that these teachers share roughly the same view on basic values, but that the methods employed by the teachers of either school differ. They also show that these two schools’ management prioritize this work differently. Conclusions that can be drawn from the results are that schools where this type of work is prioritized and where teachers work from the same point of view have greater success in conveying basic values.

FPGAs can potentially deliver tremendous acceleration in high-performance server and embedded computing applications. Whether used to augment a processor or as a stand-alone device, these reconfigurable architectures are being deployed in a large number of implementations owing to the massive amounts of parallelism offered. At the same time, a significant challenge encountered in their wide-spread acceptance is the laborious efforts required in programming these devices. The increased development time, level of experience needed by the developers, lower turns per day and difficulty involved in faster iterations over designs affect the time-to-market for many solutions. High-level synthesis aims towards increasing the productivity of FPGAs and bringing them within the reach software developers and domain experts. OpenCL is a specification introduced for parallel programming purposes across platforms. Applications written in OpenCL consist of two parts - a host program for initialization and management, and kernels that define the compute intensive tasks. In this thesis, a compilation flow to generate customized application-specific hardware descriptions from OpenCL computation kernels is presented. The flow uses Xilinx AutoESL tool to obtain the design specification for compute cores. An architecture provided integrates the cores with memory and host interfaces. The host program in the application is compiled and executed to demonstrate a proof-of-concept implementation towards achieving an end-to-end flow that provides abstraction of hardware at the front-end. / Master of Science