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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.

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Showing 1 to 2 of 2 (0.072 seconds)
1

VHDL Implementation of a Fast Adder Tree

Dacheng, Chen January 2005 (has links)
<p>This thesis discusses the design and implementation of a VHDL generator for Wallace tree with (3:2) counter modules and (2:2) counter modules to solve fast addition problem.</p><p>The basic research has been carried out by MATLAB programming environment and automatic generation of VHDL file based on the result obtained from MATLAB simulation. MODELSIM has been used for compilation and simulation of the VHDL file.</p>
Wallace tree
counter module
simulation
generator
add tree
cell array
Electrical engineering
Elektroteknik
2

VHDL Implementation of a Fast Adder Tree

Dacheng, Chen January 2005 (has links)
This thesis discusses the design and implementation of a VHDL generator for Wallace tree with (3:2) counter modules and (2:2) counter modules to solve fast addition problem. The basic research has been carried out by MATLAB programming environment and automatic generation of VHDL file based on the result obtained from MATLAB simulation. MODELSIM has been used for compilation and simulation of the VHDL file.
Wallace tree
counter module
simulation
generator
add tree
cell array
Electrical engineering
Elektroteknik

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