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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

Multiphase Optimal Response Mixed-signal Current Program Mode Controller

Alico, Jurgen 14 December 2009 (has links)
The primary focus of this thesis is to present a simple and practical implementation of an optimal-time response controller for multiphase interleaved dc-dc SMPS. This novel solution enables equal current sharing between phases not only in steady-state, but also during load transients, as well as bump-less transition between those two states. A digital voltage loop and multiple analog peak current programmed mode current loops are combined to implement a capacitor charge balance control algorithm with fairly simple hardware. This algorithm provides recovery from a disturbance in a single on-off switching action, which is performed in virtually the fastest possible time. The hybrid interface between the loops is provided through a structure combining a sample-and-hold circuit and a relatively slow successive-approximation DAC that provides control signals for all the loops in the system. Furthermore, for operation under light load conditions, the controller automatically switches into simply implemented pulse-frequency mode of operation.
2

Multiphase Optimal Response Mixed-signal Current Program Mode Controller

Alico, Jurgen 14 December 2009 (has links)
The primary focus of this thesis is to present a simple and practical implementation of an optimal-time response controller for multiphase interleaved dc-dc SMPS. This novel solution enables equal current sharing between phases not only in steady-state, but also during load transients, as well as bump-less transition between those two states. A digital voltage loop and multiple analog peak current programmed mode current loops are combined to implement a capacitor charge balance control algorithm with fairly simple hardware. This algorithm provides recovery from a disturbance in a single on-off switching action, which is performed in virtually the fastest possible time. The hybrid interface between the loops is provided through a structure combining a sample-and-hold circuit and a relatively slow successive-approximation DAC that provides control signals for all the loops in the system. Furthermore, for operation under light load conditions, the controller automatically switches into simply implemented pulse-frequency mode of operation.

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