University of Macau / Faculty of Science and Technology. / Department of Computer and Information Science

We explore quantum-resistant key establishment and hybrid encryption. We nd that while the discrete logarithm problem is e ciently solved by a quantum computer using Shor's algorithm, some instances are insecure even using classical computers. The discrete logarithm problem based on a symmetric group Sn is e - ciently solved in polynomial time. We design a PUF-based 4-round group key establishment protocol, adjusting the model to include a physical channel capable of PUF transmission, and modify adversarial capabilities with respect to the PUFs. The result is a novel group key establishment protocol which avoids computational hardness assumptions and achieves key secrecy. We contribute a hybrid encryption scheme by combining a key encapsulation mechanism (KEM) with a symmetric key encryption scheme by using two hash functions. We require only one-way security in the quantum random oracle model (QROM) of the KEM and one-time security of the symmetric encryption scheme in the QROM. We show that this hybrid scheme is IND-CCA secure in the QROM. We rely on a powerful theorem by Unruh that provides an upper bound on indistinguishability between the output of a random oracle and a random string, when the oracle can be accessed in quantum superposition. Our result contributes to the available IND-CCA secure encryption schemes in a setting where quantum computers are under adversarial control. Finally, we develop a framework and describe biometric visual cryptographic schemes generically under our framework. We formalize several security notions and de nitions including sheet indistinguishability, perfect indistinguishability, index recovery, perfect index privacy, and perfect resistance against false authentication. We also propose new and generic strategies for attacking e-BVC schemes such as new distinguishing attack, new index recovery, and new authentication attack. Our quantitative analysis veri es the practical impact of our framework and o ers concrete upper bounds on the security of e-BVC. / Includes bibliography. / Dissertation (Ph.D.)--Florida Atlantic University, 2018. / FAU Electronic Theses and Dissertations Collection

by Wong Ha Yin. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2001. / Includes bibliographical references (leaves 71-74). / Abstracts in English and Chinese. / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Traditional Payment Systems --- p.1 / Chapter 1.2 --- Electronic Payment System --- p.2 / Chapter 1.3 --- Thesis Organization --- p.4 / Chapter Chapter 2 --- Cryptographic Techniques --- p.5 / Chapter 2.1 --- Encryption and Decryption --- p.5 / Chapter 2.1.1 --- Symmetric Encryption --- p.6 / Chapter 2.1.2 --- Asymmetric or Public-Key Encryption --- p.6 / Chapter 2.2 --- RSA --- p.7 / Chapter 2.3 --- Blind Signatures --- p.8 / Chapter 2.4 --- General Computation Protocols --- p.8 / Chapter 2.5 --- Cut-and-Choose Method --- p.9 / Chapter 2.6 --- Hash Functions --- p.9 / Chapter 2.7 --- Secret Sharing --- p.10 / Chapter 2.8 --- Zero-Knowledge Proofs --- p.11 / Chapter 2.9 --- Timestamps --- p.12 / Chapter Chapter 3 --- Overview of Electronic Payment Systems --- p.13 / Chapter 3.1 --- Life Cycle --- p.13 / Chapter 3.2 --- Six Basic Requirements --- p.15 / Chapter 3.3 --- Efficiency --- p.16 / Chapter 3.4 --- History --- p.17 / Chapter Chapter 4 --- Ferguson's Single-term Off-Line Coins --- p.19 / Chapter 4.1 --- Basic Assumption and Tools --- p.19 / Chapter 4.1.1 --- Secure Hash Function --- p.19 / Chapter 4.1.2 --- Polynomial Secret Sharing Scheme --- p.20 / Chapter 4.1.3 --- Randomized Blind Signature --- p.21 / Chapter 4.2 --- The Basic Signal-term Cash System --- p.23 / Chapter 4.2.1 --- The Withdrawal Protocol --- p.24 / Chapter 4.2.2 --- The Payment Protocol --- p.26 / Chapter 4.2.3 --- The Deposit Protocol --- p.27 / Chapter Chapter 5 --- Cash with Different Denominations --- p.28 / Chapter 5.1 --- Denomination Bundling --- p.28 / Chapter 5.2 --- Coin Storage --- p.29 / Chapter Chapter 6 --- An Off-Line Transferable E-coin System --- p.32 / Chapter 6.1 --- Introduction --- p.32 / Chapter 6.2 --- The Withdrawal Protocol --- p.34 / Chapter 6.3 --- The Transfer / Payment Protocol --- p.36 / Chapter 6.4 --- The Deposit Protocol --- p.40 / Chapter 6.5 --- Expansion of Coins --- p.42 / Chapter 6.6 --- Security and privacy Analysis --- p.43 / Chapter 6.7 --- Complexity Analysis --- p.47 / Chapter 6.8 --- Conclusion --- p.49 / Chapter Chapter 7 --- A New Off-line E-check System --- p.50 / Chapter 7.1 --- Introduction --- p.50 / Chapter 7.2 --- E-checks Models --- p.51 / Chapter 7.3 --- E-Check System with Partial Privacy --- p.52 / Chapter 7.3.1 --- The Withdrawal Protocol --- p.52 / Chapter 7.3.2 --- The Payment Protocol --- p.55 / Chapter 7.3.3 --- The Deposit Protocol --- p.56 / Chapter 7.3.4 --- The Refund Protocol --- p.57 / Chapter 7.3.5 --- Protocol Discussion --- p.58 / Chapter 7.4 --- E-Check System with Unconditional Privacy --- p.59 / Chapter 7.4.1 --- The Withdrawal Protocol --- p.59 / Chapter 7.4.2 --- The Payment Protocol --- p.63 / Chapter 7.4.3 --- The Deposit Protocol --- p.64 / Chapter 7.4.4 --- The Refund Protocol --- p.65 / Chapter 7.4.5 --- Protocol Discussion --- p.67 / Chapter 7.5 --- Conclusion --- p.68 / Chapter Chapter 8 --- Conclusion --- p.69 / Reference --- p.71

by Lau Shek Kwan Mark. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2001. / Includes bibliographical references (leaves 85-86). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Historical Background --- p.2 / Chapter 1.2 --- Introduction to Autostereograms --- p.5 / Chapter 1.2.1 --- Geometrical Model --- p.5 / Chapter 1.2.2 --- IS-separation --- p.6 / Chapter 1.2.3 --- The Hidden Surfaces --- p.7 / Chapter 1.2.4 --- False Target and Echo --- p.8 / Chapter 1.3 --- The Autostereogram Generation Algorithm --- p.10 / Chapter 1.4 --- Further Applications of Autostereograms --- p.15 / Chapter 1.5 --- Organization of Thesis --- p.17 / Chapter 2 --- Analysis of Autostereograms --- p.20 / Chapter 2.1 --- IS-separation --- p.21 / Chapter 2.2 --- Autostereogram Generations --- p.25 / Chapter 2.3 --- Surface Reconstructions --- p.26 / Chapter 2.4 --- Visual Distortions --- p.28 / Chapter 2.4.1 --- Problem Model For Vertical Distortions --- p.30 / Chapter 2.4.2 --- Change of Depth Field --- p.33 / Chapter 2.4.3 --- Non-linear Distortion --- p.35 / Chapter 2.4.4 --- Lateral Distortions --- p.38 / Chapter 2.5 --- Discrete Autostereograms --- p.40 / Chapter 2.5.1 --- Truncation Problem --- p.41 / Chapter 2.5.2 --- Computer Algorithms for Autostereograms --- p.42 / Chapter 3 --- Analysis of Echoes --- p.48 / Chapter 3.1 --- Causes of Echoes --- p.49 / Chapter 3.1.1 --- Insufficient Lengths of The Periods of Repeating Patterns --- p.51 / Chapter 3.1.2 --- Overlapping of Copying Steps --- p.51 / Chapter 3.2 --- Avoidance of Type 1 Echoes --- p.52 / Chapter 3.3 --- Avoidance of Type 2 Echoes --- p.55 / Chapter 3.4 --- Autostereogram Encoding Any Surface --- p.58 / Chapter 4 --- Autostereogram as A Cryptosystem --- p.65 / Chapter 4.1 --- Introduction to Cryptography --- p.66 / Chapter 4.1.1 --- Mathematical Structure of Cryptosystems --- p.67 / Chapter 4.1.2 --- A Classical Cryptosystem´ؤSubstitution Cipher --- p.68 / Chapter 4.2 --- Autostereogram as a Cryptosystem --- p.72 / Chapter 4.2.1 --- Autostereogram as a Variation of Substitution Cipher --- p.74 / Chapter 4.2.2 --- Practical Considerations --- p.76 / Chapter 5 --- Conclusion and Future Works --- p.79 / Chapter 5.1 --- Future Works --- p.80 / Chapter A --- Excessive Removal of Copying Steps --- p.81 / Chapter B --- Publications Resulted from the Study --- p.84

Lee, Chin Ho. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2013. / Includes bibliographical references (leaves 77-82). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts also in Chinese.

Siu, Pui-Lam. / Thesis submitted in: August 2003. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references (leaves 104-109). / Abstracts in English and Chinese. / list of figures --- p.5 / list of tables --- p.7 / acknowledgements --- p.8 / abstract --- p.9 / Chapter 1. --- introduction --- p.12 / Chapter 1.1 --- Smart Card --- p.12 / Chapter 1.1.1 --- What is a smart card? --- p.12 / Chapter 1.1.2 --- How is a smart card different from the magnetic stripe card that I carry in my wallet? --- p.13 / Chapter 1.1.3 --- Why are interoperability and enforced standards crucial to widespread adoption of smart cards? --- p.13 / Chapter 1.1.4 --- Contact vs Contactless --- p.14 / Chapter 1.1.5 --- How secure and confidential contactless smart cards are? --- p.14 / Chapter 1.1.6 --- Contactless Smart Card Application Contactless smart cards are widely used in commercial fields as stored-value and secure storage cards --- p.14 / Chapter 1.1.7 --- What are the major benefits that Contactless smart cards offer to consumers? --- p.16 / Chapter 1.2 --- Design Motivation --- p.16 / Chapter 1.3 --- RF Part Interface --- p.17 / Chapter 1.4 --- Potential Advantages of Using Asynchronous Circuit --- p.19 / Chapter 1.5 --- Design Methodology for Asynchronous Circuit --- p.23 / Chapter 1.5.1 --- Difficulty and limitation of asynchronous design --- p.27 / Chapter 1.5.2 --- Asynchronous pipeline --- p.28 / Chapter 2. --- background theory --- p.32 / Chapter 2.1 --- Description of DES --- p.32 / Chapter 2.1.1 --- Outline of the Algorithm --- p.33 / Chapter 2.1.2 --- Initial Permutation --- p.35 / Chapter 2.1.3 --- Key Transformation --- p.35 / Chapter 2.1.4 --- Expansion Permutation --- p.37 / Chapter 2.1.5 --- S-box Substitution --- p.38 / Chapter 2.1.6 --- P-Box Permutation --- p.41 / Chapter 2.1.7 --- Final Permutation --- p.42 / Chapter 2.1.8 --- Decrypting DES --- p.43 / Chapter 2.1.9 --- Security of DES --- p.43 / Chapter 2.1.10 --- Weak Keys --- p.43 / Chapter 2.1.11 --- Algebraic Structure --- p.46 / Chapter 2.1.12 --- Key Length --- p.46 / Chapter 2.1.13 --- Number of Rounds --- p.48 / Chapter 2.1.14 --- Design of the S-Boxes --- p.48 / Chapter 3. --- rf part --- p.50 / Chapter 3.1 --- Power On --- p.51 / Chapter 3.2 --- Power Induction --- p.52 / Chapter 3.3 --- Limiter and Regulator --- p.54 / Chapter 3.4 --- Demodulation --- p.56 / Chapter 3.5 --- Modulation --- p.57 / Chapter 4. --- asynchronous circuit theory --- p.58 / Chapter 4.1 --- Potential Problem of Classical Asynchronous Pipeline --- p.58 / Chapter 4.2 --- The New Handshake Cell --- p.58 / Chapter 4.3 --- The Modified Asynchronous Pipeline Architecture --- p.60 / Chapter 4.4 --- Asynchronous Circuit Comparison --- p.65 / Chapter 5 --- implementation --- p.67 / Chapter 5.1 --- DES Implementation --- p.67 / Chapter 5.1.1 --- Power estimation of the asynchronous DES --- p.70 / Chapter 5.1.2 --- Modified Circuit --- p.73 / Type One --- p.73 / Type two --- p.76 / Chapter 5.1.3 --- Interface --- p.79 / Chapter 5.1.4 --- Shift Unit --- p.80 / Chapter 5.1.5 --- Multiplexer Unit --- p.82 / Chapter 5.1.6 --- Compression Unit --- p.83 / Chapter 5.1.7 --- Expansion Unit --- p.84 / Chapter 5.1.8 --- Xor Unit --- p.85 / Chapter 5.1.9 --- S_box Unit --- p.86 / Chapter 5.1.10 --- P-box unit --- p.88 / Chapter 5.1.11 --- Latch unit --- p.89 / Chapter 5.1.12 --- Transmission Unit --- p.90 / Chapter 5.2 --- Floor Plan Design --- p.90 / Chapter 6. --- result and discussion --- p.93 / Chapter 6.1 --- Simulation Result --- p.93 / Chapter 6.2 --- Measurement --- p.97 / Chapter 6.3 --- Comparison --- p.101 / Chapter 6.4 --- Conclusion --- p.101 / Chapter 7. --- reference --- p.104 / Chapter 8. --- appendix --- p.110 / Chapter 8.1 --- RF Part Implementation --- p.110 / Chapter 8.1.1 --- Full wave rectifying circuit --- p.110 / Chapter 8.1.2 --- "Limiting Circuit," --- p.111 / Chapter 8.1.3 --- Regulator circuit --- p.113 / Chapter 8.1.4 --- Demodulation circuit --- p.113 / Chapter 8.1.5 --- Simulation of the RF part --- p.115 / Chapter 8.2 --- New Technology for Designing a RF Interface --- p.117 / Chapter 8.2 --- Block Diagrams --- p.118

In The Second Theory of Cryptography Conference (TCC 2005), Boneh, Goh, and Nissim proposed a new structure of bilinear groups that have a composite order and a new cryptosystem which is intractable on a decisional problem over the subgroup in such structure [BGN05]. Their proposal, which referred to as the BGN cryptosystem by researchers, receive much attention and is quickly followed by two publications in CRYPTO'05 [BI05, OI05]. / In this thesis, the author performs in-depth study of the BGN public-key cryptosystem and existing literatures on its applications. The author observes two properties of BGN, namely the indistinguishability of the BGN ciphertexts of sum and product of two messages, and the verifiability of elements from composite prime subgroups in BGN settings. The author further proposes three new applications of BGN, namely the protocols for authentication, oblivious transfer, and proof-of-visit respectively. / The BGN cryptosystem is a dual homomorphic public-key cryptosystem that enables the evaluation of 2-DNF (disjunctive normal form) formulas on ciphertexts. In their work, Boneh et. al. also presented three applications, namely private information retrieval with reduced computational complexity, an e-voting system without non-interactive zero knowledge proofs, and a protocol for universally verifiable computation. Few number of works also produced from the BGN public-key system, include non-interactive zero-knowledge proof (NIZK), obfuscated ciphertext mixing, and signature. / Chan Yuen Yan. / "June 2006." / Adviser: Victor K. Wei. / Source: Dissertation Abstracts International, Volume: 67-11, Section: B, page: 6498. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2006. / Includes bibliographical references (p. 85-100). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts in English and Chinese. / School code: 1307.

Modular arithmetic operations (i.e., inversion, multiplication and exponentiation) are used in several cryptography applications, such as decipherment operation of RSA algorithm, Diffie-Hellman key exchange algorithm, elliptic curve cryptography, and the Digital Signature Standard including the Elliptic Curve Digital Signature Algorithm. The most important of these arithmetic operations is the modular multiplication operation since it is the core operation in many cryptographic functions. Given the increasing demands on secure communications, cryptographic algorithms will be embedded in almost every application involving exchange of information. Some of theses applications such as smart cards and hand-helds require hardware restricted in area and power resources. Cryptographic applications use a large number of bits in order to be considered secure. While some of these applications use 256-bit precision operands, others use precision values up to 2048 or 4096 such as in some exponentiation-based cryptographic applications. Based on this characteristics, a scalable multiplier that operates on any bit-size of the input values (variable precision) was recently proposed. It is replicated in order to generate long-precision results independently of the data path precision for which it was originally designed. The multiplier presented in this work is based on the Montgomery multiplication algorithm. This thesis work contributes by presenting a modified radix-4 Montgomery multiplication algorithm with new encoding technique for the multiples of the modulus. This work also describes the scalable hardware design and analyzes the synthesis results for a 0.5 ��m CMOS technology. The results are compared with two other proposed scalable Montgomery multiplier designs, namely, the radix-2 design, and the radix-8 design. The comparison is done in terms of area, total computational time and complexity. Since modular exponentiation can be generated by successive multiplication, we include in this thesis an analysis of the boundaries for inputs and outputs. Conditions are identified to allow the use of one multiplication output as the input of another one without adjustments (or reduction). High-radix multipliers exhibit higher complexity of the design. This thesis shows that radix-4 hardware architectures does not add significant complexity to radix-2 design and has a significant performance gain. / Graduation date: 2003

Computer and network security has recently become a popular subject due to the explosive growth of the Internet and the migration of commerce practices to the electronic medium. Thus the authenticity and privacy of the information transmitted and the data stored on networked computers is of utmost importance. The deployment of network security procedures requires the implementation of cryptographic functions. More specifically, these include encryption, decryption, authentication, digital signature algorithms and message-digest functions. Performance has always been the most critical characteristic of a cryptographic function, which determines its effectiveness. In this thesis, we concentrate on developing high-speed algorithms and architectures for number theoretic cryptosystems. Our work is mainly focused on implementing elliptic curve cryptosystems efficiently, which requires space- and time-efficient implementations of arithmetic operations over finite fields. We introduce new methods for arithmetic operations over finite fields. Methodologies such as precomputation, residue number system representation, and parallel computation are adopted to obtain efficient algorithms that are applicable on a variety of cryptographic systems and subsystems. Since arithmetic operations in finite fields also have applications in coding theory and computer algebra, the methods proposed in this thesis are applicable to these applications as well. / Graduation date: 1999

Three block ciphers are considered to determine how well they can be implemented on existing superscalar architectures such as the Intel Pentium. An examination of the Pentium architecture suggests that substantial performance increases can be achieved if particular rules are followed. Software libraries are written in high-level C language and low-level assembly language to produce a package of routines which achieve a near optimal performance level on a current processor architecture. The structure of each algorithm is studied to determine if it is possible to alternatively implement the algorithm such that certain steps are reordered or reduced. Using the Intel MMX architectural advances, it is observed that one algorithm benefits dramatically from a new implementation that takes advantage of MMX strengths. / Graduation date: 1999