With the increasing demand for multi-media,multi-core system architecture used in parallel processing of large amounts of data to carry out operations,in the past,large amounts of data is transferred through an independent control of DMA,and often have the following shortcomings,(1)As a result of the transmission of data is completed by reading and writing,caused the burden of memory clock singnal,(2)A large number of occupied bandwidth,caused the collision with processor by using the data bus. Based on the above shortcomings, this paper proposed an internal fast data switching mechanism through AMBA instruction by integrating the memory controller and DMA function. With the high transmission clock rate of DDR2, to achieve (1) transfer data by the original memory clock rate between memory and memory, (2) transmission between memory and device can be reached by bridge of the controller. Can significantly reduce not only the System Bus in the workload and provide the purpose of handling large amounts of data, to reduce the transmission of data on the amount of time spent and release of the right to use the Bus to other peripheral devices and to enhance the efficiency of the overall system.We also achieved the interface of SATA bridge in the controller. Through the DDR2 memory buffer to enhance the efficiency of accessing information and to provide strong type on the data buffer mechanism, can effectively reduce the number of solid-state hard disk access, the extension of its work life. According to the simulation results show that the use of traditional DMA transfer mechanism for the rapid exchange of data, compared to provide a minimum bandwidth in DDR2, you can save about 51% of transmission time, in the DDR2 maximum bandwidth available, you can save 87% of transmission time.