This thesis proposes a synthesis methodology which is capable of fault-tolerance and deadlock-free for constructing a custom NoC topology in 3D ICs. In this thesis, the processors and their communications can be synthesized simultaneously in the system-level floorplanning with fault tolerant consideration, called 3D-NoC-FT. Experimental results show that the pro-posed 3D-NoC-FT produces custom 3D NoCs with lower power dissipation than previous works. This method is also more scalable, which makes it ideal for complicated 3D NoC de-signs. Compared with the previous 3D NoC work (3D-SAL-FP) without link fault tolerance, our fault tolerant method outperforms on the average the power dissipation by 1.67X with rela-tively small overhead of latency by 17% and the number of TSV by 35%, respectively.

Deadlocks are critical events in Flexible Manufacturing Cells (FMC) that result from circular waits among a set of resources. Circular waits happen when a set of resources with finite capacity are in a permanent hold due to wait state to admit new jobs. Past literature examines the deadlock-free scheduling in FMCs considering many types of resources and techniques. This thesis proposes a new resource-oriented deadlock-free approach using a robot equipped with dual-grippers serving as a material handler in a FMC. The proposed methodology uses Constraint Programming (CP). The system performance is analyzed using different buffer configurations. Many test problems are generated to validate the developed models. The finding demonstrates that the proposed dual-gripper robot (DGR) can outperform the single-gripper robot (SGR) in many settings for FMCs. Likewise, the experience with the CP for the modeling and solving approach proposed in this research consolidates its application to FMC deadlock-free scheduling problems.

Deadlocks are critical events in Flexible Manufacturing Cells (FMC) that result from circular waits among a set of resources. Circular waits happen when a set of resources with finite capacity are in a permanent hold due to wait state to admit new jobs. Past literature examines the deadlock-free scheduling in FMCs considering many types of resources and techniques. This thesis proposes a new resource-oriented deadlock-free approach using a robot equipped with dual-grippers serving as a material handler in a FMC. The proposed methodology uses Constraint Programming (CP). The system performance is analyzed using different buffer configurations. Many test problems are generated to validate the developed models. The finding demonstrates that the proposed dual-gripper robot (DGR) can outperform the single-gripper robot (SGR) in many settings for FMCs. Likewise, the experience with the CP for the modeling and solving approach proposed in this research consolidates its application to FMC deadlock-free scheduling problems.

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A hierarchical control system is proposed for automated flexible manufacturing cells (FMC) that operate in a job shop flow setting. The control system is made up of a higher level scheduler/reactive scheduler, which optimizes the production flow within the cell, and a lower level supervisor that implements the decisions of the scheduler on the shop floor. Previous studies have regularly considered the production scheduling and the supervisory control as two separate problems. This has led to: i) deadlock-prone optimized schedules that cannot be implemented in an automated setting, ii) deadlock-free optimized schedules that lack the means to be transformed into shop floor supervisors, or iii) supervisors that can safely drive the system with no consideration for production performance. The proposed control system combines mathematical models and an insertion heuristic to solve the deadlock-free scheduling problem in job shops, a deadlock-free reactive scheduling heuristic that can revise the schedules upon the occurrence of a wide variety of disruptions, and a systematic procedure that can transform schedules into readily implementable Petri net (PN) supervisors. The integration of these modules into one control hierarchy guarantees a correct, optimized and agile behavior of the controlled system. The performances of the mathematical models, the scheduling and the reactive scheduling heuristics were evaluated by comparison to performances of previous approaches. Experimental results showed that the proposed modules performed consistently better than the other corresponding approaches. The supervisor realization procedure and the overall control architecture were validated by simulation and implementation in an experimental robotic FMC. The control system developed was capable of driving the experimental cell to satisfactorily complete the processing of different product mixes that featured complex processing routes through the cell.

A hierarchical control system is proposed for automated flexible manufacturing cells (FMC) that operate in a job shop flow setting. The control system is made up of a higher level scheduler/reactive scheduler, which optimizes the production flow within the cell, and a lower level supervisor that implements the decisions of the scheduler on the shop floor. Previous studies have regularly considered the production scheduling and the supervisory control as two separate problems. This has led to: i) deadlock-prone optimized schedules that cannot be implemented in an automated setting, ii) deadlock-free optimized schedules that lack the means to be transformed into shop floor supervisors, or iii) supervisors that can safely drive the system with no consideration for production performance. The proposed control system combines mathematical models and an insertion heuristic to solve the deadlock-free scheduling problem in job shops, a deadlock-free reactive scheduling heuristic that can revise the schedules upon the occurrence of a wide variety of disruptions, and a systematic procedure that can transform schedules into readily implementable Petri net (PN) supervisors. The integration of these modules into one control hierarchy guarantees a correct, optimized and agile behavior of the controlled system. The performances of the mathematical models, the scheduling and the reactive scheduling heuristics were evaluated by comparison to performances of previous approaches. Experimental results showed that the proposed modules performed consistently better than the other corresponding approaches. The supervisor realization procedure and the overall control architecture were validated by simulation and implementation in an experimental robotic FMC. The control system developed was capable of driving the experimental cell to satisfactorily complete the processing of different product mixes that featured complex processing routes through the cell.

In the pursuit for ever-increasing compute power, and with Moore's law slowly coming to an end, high-performance computing started to scale-out to larger systems. Alongside the increasing system size, the interconnection network is growing to accommodate and connect tens of thousands of compute nodes. These networks have a large influence on total cost, application performance, energy consumption, and overall system efficiency of the supercomputer. Unfortunately, state-of-the-art routing algorithms, which define the packet paths through the network, do not utilize this important resource efficiently. Topology-aware routing algorithms become increasingly inapplicable, due to irregular topologies, which either are irregular by design, or most often a result of hardware failures. Exchanging faulty network components potentially requires whole system downtime further increasing the cost of the failure. This management approach becomes more and more impractical due to the scale of today's networks and the accompanying steady decrease of the mean time between failures. Alternative methods of operating and maintaining these high-performance interconnects, both in terms of hardware- and software-management, are necessary to mitigate negative effects experienced by scientific applications executed on the supercomputer. However, existing topology-agnostic routing algorithms either suffer from poor load balancing or are not bounded in the number of virtual channels needed to resolve deadlocks in the routing tables. Using the fail-in-place strategy, a well-established method for storage systems to repair only critical component failures, is a feasible solution for current and future HPC interconnects as well as other large-scale installations such as data center networks. Although, an appropriate combination of topology and routing algorithm is required to minimize the throughput degradation for the entire system. This thesis contributes a network simulation toolchain to facilitate the process of finding a suitable combination, either during system design or while it is in operation. On top of this foundation, a key contribution is a novel scheduling-aware routing, which reduces fault-induced throughput degradation while improving overall network utilization. The scheduling-aware routing performs frequent property preserving routing updates to optimize the path balancing for simultaneously running batch jobs. The increased deployment of lossless interconnection networks, in conjunction with fail-in-place modes of operation and topology-agnostic, scheduling-aware routing algorithms, necessitates new solutions to solve the routing-deadlock problem. Therefore, this thesis further advances the state-of-the-art by introducing a novel concept of routing on the channel dependency graph, which allows the design of an universally applicable destination-based routing capable of optimizing the path balancing without exceeding a given number of virtual channels, which are a common hardware limitation. This disruptive innovation enables implicit deadlock-avoidance during path calculation, instead of solving both problems separately as all previous solutions.

In the pursuit for ever-increasing compute power, and with Moore's law slowly coming to an end, high-performance computing started to scale-out to larger systems. Alongside the increasing system size, the interconnection network is growing to accommodate and connect tens of thousands of compute nodes. These networks have a large influence on total cost, application performance, energy consumption, and overall system efficiency of the supercomputer. Unfortunately, state-of-the-art routing algorithms, which define the packet paths through the network, do not utilize this important resource efficiently. Topology-aware routing algorithms become increasingly inapplicable, due to irregular topologies, which either are irregular by design, or most often a result of hardware failures. Exchanging faulty network components potentially requires whole system downtime further increasing the cost of the failure. This management approach becomes more and more impractical due to the scale of today's networks and the accompanying steady decrease of the mean time between failures. Alternative methods of operating and maintaining these high-performance interconnects, both in terms of hardware- and software-management, are necessary to mitigate negative effects experienced by scientific applications executed on the supercomputer. However, existing topology-agnostic routing algorithms either suffer from poor load balancing or are not bounded in the number of virtual channels needed to resolve deadlocks in the routing tables. Using the fail-in-place strategy, a well-established method for storage systems to repair only critical component failures, is a feasible solution for current and future HPC interconnects as well as other large-scale installations such as data center networks. Although, an appropriate combination of topology and routing algorithm is required to minimize the throughput degradation for the entire system. This thesis contributes a network simulation toolchain to facilitate the process of finding a suitable combination, either during system design or while it is in operation. On top of this foundation, a key contribution is a novel scheduling-aware routing, which reduces fault-induced throughput degradation while improving overall network utilization. The scheduling-aware routing performs frequent property preserving routing updates to optimize the path balancing for simultaneously running batch jobs. The increased deployment of lossless interconnection networks, in conjunction with fail-in-place modes of operation and topology-agnostic, scheduling-aware routing algorithms, necessitates new solutions to solve the routing-deadlock problem. Therefore, this thesis further advances the state-of-the-art by introducing a novel concept of routing on the channel dependency graph, which allows the design of an universally applicable destination-based routing capable of optimizing the path balancing without exceeding a given number of virtual channels, which are a common hardware limitation. This disruptive innovation enables implicit deadlock-avoidance during path calculation, instead of solving both problems separately as all previous solutions.