Delay variability poses a formidable challenge in both design and test of nanometer circuits. While process parameter variability is increasing with technology scaling, as circuits are becoming more complex, the dynamic or vector dependent variability is also increasing steadily. In this research, we develop solutions to incorporate the effect of delay variability in delay testing. We focus on two different applications of delay testing. In the first case, delay testing is used for testing the timing performance of a circuit using path based fault models. We show that if dynamic delay variability is not accounted for during the path selection phase, then it can result in targeting a wrong set of paths for test. We have developed efficient techniques to model the effect of two different dynamic effects namely multiple-input switching noise and coupling noise. The basic strategy to incorporate the effect of dynamic delay variability is to estimate the maximum vector delay of a path without being too pessimistic. In the second case, the objective was to increase the defect coverage of reliability defects in the presence of process variations. Such defects cause very small delay changes and hence can easily escape regular tests. We develop a circuit that facilitates accurate control over the capture edge and thus enable faster than at-speed testing. We further develop an efficient path selection algorithm that can select a path that detects the smallest detectable defect at any node in the presence of process variations. / text

Projekto tikslas – sukurti sistemą, skirtą schemų testinių atvejų atrinkimui naudojant „juodos dėžės“ modelius ir jiems pritaikytus gedimų modelius. Vykdant projektą buvo atlikta kūrino būdų ir technologijų analizė. Sistemos architektūra buvo kuriama atsižvelgiant į reikalavimą, naudoti schemų modelius, kurie yra parašyti c programavimo kalba. Buvo atlikta schemų failų integravimo efektyvumo analizė, tiriamos atsitiktinio testinių atvejų generavimo sekos patobulinimo galimybės, "1" pasiskirstymo 5taka atsitiktinai generuojam7 testini7 atvej7 kokybei. Tyrim7 rezultatai: • Schemų modelių integracijos tipas mažai įtakoja sistemos darbą. • Pusiau deterministinių metodų taikymas parodė, jog atskirų žingsnių optimizacija nepagerina galutinio rezultato. • "1" pasiskirstymas atsitiktinai generuojamose sekose turi įtaką testo kokybei ir gali būti naudojamas testų procesų pagerinimui. / Project objective – to develop a system, which generates functional tests for non-scan synchronous sequential circuits based on functional delay models. During project execution, the analysis of design and technology solutions was performed. The architecture of the developed software is based on the requirement to be able to use the models of the benchmark circuits that are written in C programming language. Analysis of the effectiveness of the model file integration, possibilities of improving random test sequence generation and the influence of distribution of „1“ in randomly generated test patterns was performed. The results of the analysis were: • Type of the model file integration has little effect when using large circuit models. • The implementation of semi deterministic algorithms showed that the optimisation of separate steps by construction of test subsequences doesn’t improve the final outcome. • The distribution of „1“ in randomly generated test patterns has effect on the fault coverage and can be used to improve test generation process.