This dissertation presents a dynamic reconfigurable control strategy based on the Direct Machining And Control (DMAC) research at Brigham Young University. A reconfigurable framework is proposed which will allow a machine tool to be controlled by a variety of applications and control laws. This Reconfigurable Mechanism for Application Control (RMAC) paradigm uses a hierarchical architecture to configure a mechanism into a device driver for direct control by an application like CAD/CAM. The RMAC paradigm is one of a mechanism device driver assigned to each mechanism class or model, and uses only the master model to control the mechanism. The traditional M&G code language is no longer necessary since motion entities are passed directly to the mechanism. The design strategy of using dynamic-link libraries (DLL) to form a mechanism device driver permits a mechanism to assume different operating configurations, depending on the number of axes and machine resolution. For example, the machine can perform as a material removal machine in one instant, and then, by loading a new device driver, act as a Coordinate Measuring Machine (CMM). This strategy is possible because RMAC is a software and networked-based control architecture. Both the CAD/CAM planning software and the real-time control software reside on the same PC. The CAM process plan can thus directly control the machine without need for process plan decomposition into the forms supported by the controller. The architectural framework is explained in detail and the methodology for control software reconfiguration into a device driver is presented. For demonstration purposes two device drivers are implemented on a prototype machine to demonstrate feasibility and usefulness.

Modern computer systems require efficient data transfers involving memory in order to get the best possible performance. However, even the most optimized CPUs take too long to access memory regions, which takes time away from doing the typical computations that a CPU is designed to do. To solve this, Direct Memory Access (DMA) is used, which allows peripherals and other hardware accelerators, such as stand-alone DMA Controllers (DMACs), to read and write memory without CPU intervention. However, DMA introduces security problems in which attackers are able to leak data and overwrite critical system components by bypassing typical operating system security mechanisms. This thesis presents a case study to model as well as verify DMA device driver code in HOL4, which is an interactive theorem prover (ITP) used for machine-checked verification. This thesis verifies parts of Intel's IXGBE X550 device driver, which is a complex, 10 Gbit Network Interface Card (NIC). This verification takes the first significant step towards proving that the DMA device driver configures the DMA device such that it preserves memory isolation, which ensures that only memory that is intended to be readable and writable will be accessed. This thesis also provides a formal method to verify that a loop terminates under all possible cases. This can be used to further verify the correctness of a DMA driver. These contributions allow for the overall increased security of memory when using DMA device drivers that are verified by this approach, leading to the hindrance of attacks on systems utilizing DMA. / Master of Science / Modern computer systems use Direct Memory Accesses (DMAs) in order to offload the CPU from doing memory transfers. However, this poses the problem that the CPU is not able to monitor every memory access made through DMA. This can lead to attackers utilizing vulnerabilities in the device drivers used to perform DMA operations. This thesis addresses this problem by modeling and verifying properties of a device driver that will prove that the driver configures DMA such that it is isolated. This thesis also models and verifies a loop to ensure that it terminates, further verifying the correctness of a function in a device driver. These contributions are significant because they allow for increased security of a computer system's memory, reducing the likelihood of attacks.

This work deals with the design and implementation of high-speed communication interfaces into FPGA chip and their utilizing for image transmission and processing. In the implementation part has been created PCI Express endpoint device, which provides data transfers between the FPGA chip and computer RAM memory. As a source of image data for further processing was connected the Unicam M621 camera throught the Ethernet interface to FPGA chip. The project was implemented on the Xilinx SP605 development board. Using both of the the interfaces were demonstrated on the application of edge detection using Sobel operator. The PCI Express endpoint device driver for the Linux operating system and a simple application interface in C language was also created within this project.

There is a family of COMBO cards used for netork monitoring acceleration being developed on the Liberouter project, which is the CESNET's research activity. These cards are equipped with Xilinx's programmable field array. To enable usage of classic tools for network monitoring and management, not only application specific tools, it is necessary to implement network interface card on the platform, that realizes packet reception and transmission through the standard Linux kernel interface. This thesis describes the design and implementation of network interface card's key components. Those are DMA controller and Linux device driver.

Professional audio processing systems such as digital musical instruments, audiomixers, etc. must operate with very tight constraints on overall processing latencyand CPU performance. Consequently, traditional implementations are still mostlybased on specialized hardware like Digital Signal Processors (DSP) and Real-TimeOperating Systems (RTOS) to meet such requirements. However, such systems areminimalistic in nature and they lack many features (e.g. network connectivity, widehardware support, etc.) that a general-purpose operating system such as Linuxoffers. Linux is a very popular choice for the operating system used in embeddeddevices, and many developers have started to use it for designing real-time systemswith relaxed timing constraints. However, none of the available solutions using astandard Linux kernel can satisfy the low-latency requirements of professional audiosystems.In this thesis, a dual kernel approach is employed to enable an embedded Linuxsystem to process audio with low roundtrip latency. The solution is developed usingthe Xenomai framework for real-time computation, which is based on a techniqueknown as interrupt pipeline (I-pipe). I-Pipe enables interrupt virtualization througha micro-kernel running between the Linux kernel and the interrupt controller hardware.The designed system includes an x86 Atom System-on-Chip (SoC), an XMOSmicrocontroller and audio converters to and from the analog domain. Custom kerneldrivers and libraries have been developed to expose the audio programming functionalitiesto programs running in user-space. As a result, the system can achieverobust real-time performance appropriate for professional audio applications, andat the same time it has all the advantages of a traditional Linux solution such ascompatibility with external devices and ease of programming. The real-time capabilityis measured by evaluating the performance in terms of worst case responsetime of the real-time tasks in comparison to the same metrics obtained under astandard Linux kernel. The overall roundtrip latency of audio processing is showedto be improved by almost an order of magnitude (around 2.5ms instead of 20ms). / Profesionella system för ljudbearbetning, som digitala musikinstrument, mixerbord,etc, arbetar med väldigt hårda krav på tidfördröjning och CPU-prestanda. Som enkonsekvens har dessa system traditionellt implementerats på specialiserad hårdvarasom specifika DSP-processor och speciella realtidsoperativsystem. Den typen avsystem är till sin natur minimalistiska och saknar många funktioner (till exempelnätverk och brett stöd för olika hårdvaror) som mer generella operativsystem,som Linux, kan erbjuda. Linux är ett väldigt populärt val av operativsystem förinbyggda system och många utvecklare har även börjat använda det till realtidssystemmed mindre hårda tidskrav. Det finns dock idag inte någon lösning med enstandard-linuxkärna som kan tillfredsställda de krav på låg fördröjning som krävsför användning i profesionella ljudsystem.I det här examensarbetet används en dubbelkärneuppsättning för att ge ettinbyggt Linuxsystem möjlighet att bearbeta digitalt ljud med låg fördröjning. Lösningenanvänder Xenomai-ramverket för realtidsberäkningar baserat på en teknikkallad interrupt pipeline (I-pipe). I-pipe ger möjlighet att virtualisera interruptgenom en mikrokärna som körs som ett lager mellan Linuxkärnan och hårdvaransinterruptcontroller.Det resulterande systemet inkluderar ett x86 Atom-enchipssystem, en XMOSmicrocontroller, och ljudkonverterare till och från analoga ljud in- och utgångar.Drivrutiner och bibliotek utvecklas för att ge direkt tillgång till ljudfunktionerfrån applikationer. Systemet ges därmed robust realtidsprestanda som gör detlämpligt för profesionella ljudtillämpningar samtidigt som det behåller alla fördelarfrån ett traditionellt Linuxsystem, som kompabilitet med extern hårdvara och enklareapplikationsutveckling. Systemets realtidsprestanda utvärderas som den maximalauppmätta tidfördröjning vid realtidsberäkningar jämfört med motsvarandeberäkningar på en standardlinuxkärna. Resultaten visade på en förbättring på nästanen storleksordning (ca 2,5ms mot 20ms).

Thema dieser Arbeit ist die Entwicklung eines Kommunikationsteilsystems fuer das Experimentiersystem CHEOPS zur Ermoeglichung einer Interobjektkommunika- tion zwischen Objekten auf dem gleichen bzw. verschiedenen Systemen. Ausgangspunkte stellen dabei eine verfuegbare Implementation eines Ethernet- Treibers der Kartenfamilie WD80x3 fuer MS-DOS, eine geforderte Kommunikations- moeglichkeit mit UNIX-Prozessen sowie die dort benutzbaren Protokoll-Familien dar. Die Arbeit beschaeftigt sich mit der Analyse und Konzipierung des Ethernet- Treibers sowie der Internet-Protokoll-Familie fuer CHEOPS als auch deren Implementation resultierend in einem minimalen Grundsystem. Weiterhin wird ein erster Entwurf fuer ein spaeter weiterzuentwickelndes bzw. zu vervoll- staendigendes Netz-Interface vorgeschlagen und durch eine Beispiel-Implemen- tierung belegt.

Thema dieser Arbeit ist die Entwicklung eines Kommunikationsteilsystems fuer das Experimentiersystem CHEOPS zur Ermoeglichung einer Interobjektkommunika- tion zwischen Objekten auf dem gleichen bzw. verschiedenen Systemen. Ausgangspunkte stellen dabei eine verfuegbare Implementation eines Ethernet- Treibers der Kartenfamilie WD80x3 fuer MS-DOS, eine geforderte Kommunikations- moeglichkeit mit UNIX-Prozessen sowie die dort benutzbaren Protokoll-Familien dar. Die Arbeit beschaeftigt sich mit der Analyse und Konzipierung des Ethernet- Treibers sowie der Internet-Protokoll-Familie fuer CHEOPS als auch deren Implementation resultierend in einem minimalen Grundsystem. Weiterhin wird ein erster Entwurf fuer ein spaeter weiterzuentwickelndes bzw. zu vervoll- staendigendes Netz-Interface vorgeschlagen und durch eine Beispiel-Implemen- tierung belegt.