A formidable challenge in the present multi-step Cu CMP process, employed in the ultra-large-scale integration (ULSI) technology, is the control of wafer surface non-uniformity, which primarily is due to dielectric erosion and Cu dishing. In contrast with the earlier experimental and semi-theoretical investigations, a systematic way of characterizing and modeling dielectric erosion in both single- and multi-step Cu CMP processes is presented in this paper. Wafer- and die-level erosion are defined, and the plausible causes of erosion at each level are identified in terms of several geometric and physical parameters. Experimental and analytical means of determining the model parameters are also outlined. The local pressure distribution is estimated at each polishing stage based on the evolving pattern geometry and pad deformation. The single-step model is adapted for the multi-step polishing process, with multiple sets of slurry selectivities, applied pressure, and relative velocity in each step. Finally, the effect of slurry-switching point on erosion was investigated for minimizing dielectric erosion in the multi-step Cu CMP. Based on the developed multi-step erosion model, the physical significance of each model parameter on dielectric erosion is determined, and the optimal polishing practices for minimizing erosion in both multi-step and single-step polishing are suggested. / Singapore-MIT Alliance (SMA)