It can be expected that digital controllers will be increasingly used in low voltage, high-current and high frequency voltage regulator modules (VRMs) where conventional analog controllers are currently preferred because of the cost and performace reasons. However, there are still remaining two significant challenges for the spread of the digital control techniques: quantization effects and the delay effects. Quantization effects might introduce the limit cycle oscillations (LCOs) to the converter, which will generate the stability issues. Actually, LCOs can not be totally eliminated theoretically. One way to reduce the possibilities of LCOs is to employ a high resolution Digital Pulse-Width-Modulator (DPWM). However, designing such a DPWM which can meet the requirements of VRMs application requires ultra-high system clock frequency, up to several GHz. Such high frequency is impractical due to huge power consumption. Hybrid DPWM might be an alternative solution but will occupy large silicon area. Single phase digital constant on-time modulation method is another good candidate to improve the DPWM resolution without adding too much cost. However, directly extending this method to multi-phase application, which is the prevalent structure in VRMs application, will introduce some issues. With more phases in parallel, the duty cycle resolution will drop more. To solove the mentioned issue, this work proposed a multi-phase digital constant on-time modulation method. The proposed method will control the control voltage to alternate between two adjacent values, or dither, within one switching period. The outcome is that the phase duty cycle's resolution is improved and independent on phase number. Compared with conventional constant frequency modulation method, the proposed method can achieve about 10 times higher duty cycle resolution for the VRM application. The effectiveness of the proposed method is verified by the simulation as well as the experiment results. Delay effect is another concern for the digital controlled VRMs. There exist several types of delays in the digital feedback loop, including the ADC conversion delay, digital compensator calculation delay, DPWM delay as well as some propagation delays. Usually these delays are inside the digital controller and it is hard to know the exact values. There are several papers talking about the small signal models of the digital voltage mode control. These models are valid only if all the delay terms are known exactly since each delay is considered separately. Actually, this process is not easy. Moreover, there is no literature talking about the complete small signal model of the digital VRMs. But in reallity, different implementations of the sampling process will give different impacts to the loop. This work proposed the small signal signal models of digital VRMs. The analysis is based on the assumptions that DPWM is a double-edge modulation and the sampling instants are aligned with the middle of one phase's off time. At first, the conversion and calculation delay is neglected. The focus of the modeling is on the small signal model of the current sampling methods and the DPWM delay. This model is valid for those digital controllers which have fast ADC and fast calculation capabilities. It is shown that even with a "fast" controller, the current sampling and DPWM might introduce some delay to the loop. After that, the conversion and calculation delay are considered into the modeling. Two time periods, T1ff and T1rr, are employed to describe the total delay effects in the control loop. It is observed that the total delay in the loop is integral times of sampling periods, which is never reported by any other literatures. Therefore, the proposed model only includes one delay term and the value of this delay can be found through a pre-determined lookup table. Finally, the complete small signal model of the digital VRMs considering the conversion and calculation delay is proposed. This model is helpful for the researchers to find the delay effects in their control loop based on the range of the total physical delay in the controller. With the derived small signal mondels of digital VRMs, the design guildeline for AVP control are presented. The digital active-droop control is employed and it borrows the concept of constant output impedance control from the analog world. Two design examples are provided for the verification. / Master of Science

Abstract This thesis describes the development of a high precision time-to-digital converter (TDC) in which the conversion is based on a counter and three-stage stabilised delay line interpolation developed in this work. The biggest design challenges in the design of a TDC are related to the fact that the arrival moment of the hit signals (start and stop) is unknown and asynchronous with respect to the reference clock edges. Yet, the time interval measurement system must provide an immediate and unambiguous measurement result over the full dynamic range. It must be made sure that the readings from the counter and the interpolators are always consistent with very high probability. Therefore, the operation of the counter is controlled with a synchronising logic that is in turn controlled with the interpolation result. Another synchronising logic makes it possible to synchronise the timing signals with multiphase time-interleaved clock signals as if the synchronising was done with a GHz-level clock, and enables multi-stage interpolation. Multi-stage interpolation reduces the number of delay cells and registers needed. The delay line interpolators are stabilised with nested delay-locked loops, which leads to good stability and makes it possible to improve single-shot precision with a single look-up table containing the integral nonlinearities of the interpolators measured at the room temperature. A multi-channel prototype TDC was fabricated in a 0.6 μm digital CMOS process. The prototype reaches state-of-the-art rms single-shot precision of better than 20 ps and low power consumption of 50 mW as an integrated TDC.

In astronomy, interferometry by ground-based telescopes offers the greatest angular resolution. However, the Earth´s atmosphere distorts the incident wavefront from a celestial object, leading to blurring and signal loss. It also restricts the transmission of specific wavelengths within the electromagnetic spectrum. Space-based interferometers would mitigate atmospheric obstruction and potentially enable even higher angular resolutions. The main challenge of implementing space-based interferometry is the necessity of matching the light´s optical path differences at the telescopes within the coherence length of the light utilizing physical delay lines. This thesis explores the potential realization of digital delay lines via heterodyne interferometry. The technique generates a heterodyne beat note at the frequency difference between the incident stellar light and a reference laser in the radio regime, permitting digitization of the delay line while preserving the phase information for image reconstruction. The primary objective of the thesis is to advance the field of astronomy by constructing a testbed environment for investigating future space-based heterodyne interferometry in the NIR light range. It requires the achievement of two main tasks. Firstly, a laboratory starlight simulator is developed to simulate a distant star´s wavefront appearance as it reaches telescopes on or around Earth. The consequent starlight simulator contains an optical assembly that manifests a point source in NIR light, aligned with a mirror collimator’s focal point, transforming the wavefront from spherical to planar. Secondly, a fiber optical circuit with interference capability is constructed, consisting of a free-space optical delay line and a polarization-controlled custom-sized fiber. The delay line matches the optical paths within the light's coherence length, while the polarization controller optimizes interference visibility. The completion of the tasks establishes the foundation to investigate space-based heterodyne interferometry in the NIR light with the potential implementation of delay line digitization.