Thesis (M.S.)--Oregon State University, 2006. / Printout. Includes bibliographical references (leaves 104-107). Also available on the World Wide Web.

Thesis (M.S.)--University of Wisconsin--Madison, 1969. / eContent provider-neutral record in process. Description based on print version record.

This thesis treats broad aspects of voltage-to-digital converter design. Particular emphasis is placed on material related to designing a converter to satisfy a set of converter specifications that is given in the introduction of the thesis. The converter design is first considered in terms of basic conversion techniques. One technique, known as"successive approximation,” seems best to satisfy the requirements of the design specifications. The “successive-approximation" voltage-to-digital converter requires that its input voltage be compared to a voltage that is systematically generated within the converter. The voltage generated within the converter is derived from digital information. When the internal voltage equals the external applied voltage, a conversion is accomplished and the converter can output its digital information as the numerical equivalent of its input voltage. A major part of the thesis is concerned with basic approaches that might be used in generating a voltage from digital information in a manner that is fast, accurate, stable, and compatible with a fast, accurate, stable comparison operation. Another major part of the thesis presents analysis of specific circuits that are used in the construction of a converter designed to satisfy the introduction’s specifications. A report on the performance of a converter built with the just mentioned circuits is included. / Master of Science

In an increasingly digital world, the need for high speed and high fidelity analog-to-digital (A/D) converters is paramount. Performance improvements in electronic A/Ds have not kept pace with demand, hence the need to consider alternative technologies. One such technology is photonics, as it takes advantage of optical sampling, high speed optical switches and low cross-talk interconnects. Optical sampling derives its advantage from the application of ultra low timing jitter (<100fs) mode locked lasers utilised to provide high speed clock pulses. In this thesis the feasibility and simulated performance of three different types of photonic oversampled A/D converters was investigated. The first, and simplest design is that of oversampled pulse-code-modulation (PCM), where a 2-level photonic comparator is used to sample the analog input at a frequency much greater than the Nyquist frequency. Subsequent low pass filtering produces a digital representation of the input. The other two architectures that were investigated are the first-order sigma-delta and error diffusion, which add one level of error correction to the PCM technique. These two architectures require the functional elements of a subtractor, comparator and delay. The photonic comparator and subtractor functionality was provided by Self-Electro-Optic Effect devices (SEED) based upon multiple quantum well (MQW) p-i-n devices. To facilitate calculation of the performance of the different architectures and aid in device design, a simulation of SEED operation based upon experimental data was developed. The simulation’s accuracy was demonstrated by agreement with the results from experimental S-SEED switching and optical subtraction. To emphasize the utility of the model, the simulation was subsequently used to demonstrate tristability of an S-SEED and critical slowing down in a bistable S-SEED. These effects were experimentally verified. To provide enhanced comparator contrast ratio and subtractor dynamic range, resonantly enhanced microcavity multiple quantum well (MQW) p-i-n devices were designed and grown by MOCVD. The operation of the subtractor and comparator was experimentally demonstrated and utilising temperature tuning, optimised performance was achieved with devices from the same wafer. Furthermore, the inclusion of gain was shown to improve the subtractor performance to that demanded by the sigma-delta. The constraints on each architecture imposed by the unipolar nature of the light intensity were derived and the sigma delta architecture was shown to be superior to the error diffusion for a photonic implementation. Using the numerical simulation based upon experimentally derived data, the entire sigma delta architecture was simulated to calculate the expected performance. The signal-to-quantisation-noise ratio (SQNR) was calculated as a function input amplitude and a peak SQNR of 54dB was obtained for an oversampling ratio of 100. / http://library.adelaide.edu.au/cgi-bin/Pwebrecon.cgi?BBID=1283979 / Thesis (Ph.D.) -- University of Adelaide, School of Chemistry and Physics, 2007

Call number: LD2668 .T4 1985 D63 / Master of Science

Stress sensitivity of a 16 - bit D/A converter in a molded plastic DIP has been studied. Device performance was shown to change as a function of package stress. The effects of die position in the package and the presence or absence of die coat on package stress and device performance were determined. Finite element methods were employed for system analysis. Device stress sensitivity was attributed to diffused bit transistors and the mechanism assigned to nonuniformity of stress on the device bit transistors. Die coat (silicone gel) was shown to reduce normal and shear stresses and have little or no effect on X-axial stresses. Lowering the die in the package was shown to increase the X-axial stress uniformity from the die center to edge for die-coated parts and alter the value of shear stresses near the die edge for parts without die coat.

The purpose of this research is to determine the linearity and monotonicity of the THS5651IDW digital to analog converter (DAC), a prototype of the future Texas Instruments TLV5651, 10-bit, 125 MHz communication DAC. Testing was conducted at the Texas Instruments facility on Forest Lane, Dallas, Texas. Texas Instruments provided test equipment, software and laboratory space to obtain test data. Analysis of the data found the DAC to be monotonic since the magnitude of the differential nonlinearity (DNL) was less than ± 1 least significant bit (LSB) and the integral nonlinearity (INL) was less than ± 0.5 LSB. The study also showed that the DAC has primarily negative DNL although the DNL is well within the desired specification.

Wang Hongwei. / "February 2001." / Thesis (Ph.D.)--Chinese University of Hong Kong, 2001. / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. Ann Arbor, MI : ProQuest Information and Learning Company, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Mode of access: World Wide Web. / Abstracts in English and Chinese.

Finally, another new 0.5V fully differential wideband amplifier, which can be used in the wideband modulator, has been proposed. The gate-input two-stage amplifier employs a DC common-mode feedback circuit that uses a Miller-amplified capacitor for its frequency compensation. With the proposed technique, the power consumption of the low-voltage amplifier is drastically reduced. / Furthermore, a new dynamic CM level shifting technique for low-voltage CT delta-sigma modulators that employ a return-to-open feedback DAC is reported in the thesis. The technique maintains a stable CM level at the amplifier's inputs for this type of modulators. Simulation results show that it improves the modulator's SNDR by 11%. / In this thesis, we present research works on developing a low-voltage delta-sigma modulator with a wide signal bandwidth. Specifically, a 0.5V complex low-pass continuous-time (CT) third-order delta-sigma modulator that has a single-sided signal bandwidth of 1MHz, targeting for application in Bluetooth receivers, is presented without using any internal voltage boosting techniques which are potentially harmful to the reliability of the device. The wide bandwidth of the modulator at this low supply voltage is enabled by a special common-mode (CM) level arrangement in the system level and by new low-voltage amplifies. Realized in a 0.13mum CMOS process the proposed modulator achieves a 61.9-dB peak signal-to-noise-and-distortion ratio at the nominal supply of 0.5V with 3.4mW consumption, and occupies an active area of 0.9mm2. The modulator achieves the best figure-of-merit among its class. / The development of low-voltage design techniques for analog circuits has recently received a lot of attention due to the continuous shrinking of the supply voltage in modern CMOS technologies, which is projected to reduce to 0.5V for low power applications within ten years in the International Technology Roadmap for Semiconductor. This thesis focuses on developing circuit techniques for low-voltage delta-sigma modulator, a functional block that is widely used in mixed-signal integrated circuits. Several delta-sigma modulators operating at supply voltages below 0.9V have been reported in the open literature. However, none of them supports a signal bandwidth wider than 100kHz with a reasonable performance. / He, Xiaoyong. / Adviser: Kong Pang Pun. / Source: Dissertation Abstracts International, Volume: 72-01, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2010. / Includes bibliographical references (leaves 104-111). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. Ann Arbor, MI : ProQuest Information and Learning Company, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. Ann Arbor, MI : ProQuest Information and Learning Company, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

Thesis (Ph. D.)--Oregon State University, 2007. / Printout. Includes bibliographical references (leaves 77-81). Also available on the World Wide Web.