<p>In this thesis work, a design of RF down-conversion mixer for WLAN standard, such as Wi-Fi or Bluetooth is presented. The target technology is 0.35um CMOS process. Several mixer topologies are analyzed and simulated at the schematic level using the Cadence Spectre-RF software. The active double balanced mixer is chosen for the ultimate implementation. For this mixer simulation results from schematic level to layout level are presented and discussed in detail. </p><p>To build an RF front-end, the complete mixer is integrated with an available LNA block. The performance of the front-end is evaluated as well. The obtained simulation results satisfy the specification for Wi-Fi standard. </p><p>Since the RF front-end is designed for testability, the fault simulation is incorporated as well. So the performance of the front end is also evaluated for so called “spot defects”, typical of CMOS technology. They are modeled using resistive shorts or opens in the circuit.</p>

In this thesis work, a design of RF down-conversion mixer for WLAN standard, such as Wi-Fi or Bluetooth is presented. The target technology is 0.35um CMOS process. Several mixer topologies are analyzed and simulated at the schematic level using the Cadence Spectre-RF software. The active double balanced mixer is chosen for the ultimate implementation. For this mixer simulation results from schematic level to layout level are presented and discussed in detail. To build an RF front-end, the complete mixer is integrated with an available LNA block. The performance of the front-end is evaluated as well. The obtained simulation results satisfy the specification for Wi-Fi standard. Since the RF front-end is designed for testability, the fault simulation is incorporated as well. So the performance of the front end is also evaluated for so called “spot defects”, typical of CMOS technology. They are modeled using resistive shorts or opens in the circuit.

Direct-Down Conversion (DDC) principle based transceiver architectures are of interest to meet the diverse needs of present and future wireless systems. DDC transceivers have a simple structure with fewer analog components and offer low-cost, flexible and multi-standard solutions. However, DDC transceivers have certain circuit impairments affecting their performance in wide-band, high data rate and multi-user systems. IQ imbalance is one of the problems of DDC transceivers that limits their image rejection capabilities. Compensation techniques for frequency independent IQI arising due to gain and phase mismatches of the mixers in the I/Q paths of the transceiver have been widely discussed in the literature. However for wideband multi-channel transceivers, it is becoming increasingly important to address frequency dependent IQI arising due to mismatches in the analog I/Q lowpass filters. A hardware-efficient and standard independent digital estimation and compensation technique for frequency dependent IQI is introduced which is also capable of tracking time-varying IQI changes. The technique is blind and adaptive in nature, based on the second order statistical properties of complex random signals such as properness/circularity. A detailed performance analysis of the introduced technique is executed through computer simulations for various real-time operating scenarios. A novel technique for finding the optimal number of taps required for the adaptive IQI compensation filter is proposed and the performance of this technique is validated. In addition, a metric for the measure of properness is developed and used for error power and step size analysis. / Master of Science