La théorie, la conception, l'optimisation et la caractérisation d'amplificateurs distribués en technologie TBDH InP 0,7 µm, pour les systèmes de communications optiques à 100 Gbit/s, sont présentés. Nous montrons comment l'exploitation adaptée du concept d'amplificateur distribué avec une technologie de transistors bipolaires à produit vitesse-amplitude élevé a permis la réalisation d'un driver de modulateur électro-optique fournissant une amplitude différentielle d'attaque de 6,2 et 5,9 Vpp, à 100 et 112 Gbit/s, respectivement, avec une qualité de signal élevée. Ce circuit établit ainsi le record de produit vitesse-amplitude à 660 Gbit/s.V sur tranche et 575 Gbit/s.V en module hyperfréquence. Dans le cadre du projet Européen POLYSYS, il a été associé à un laser accordable et un modulateur pour la réalisation d'un module transmetteur optoélectronique compact, démontrant des performances avançant l'état de l'art des communications optiques courtes distances à 100 Gbit/s. / The theory, design, optimisation and characterisation of distributed amplifiers in 0.7-µm InP DHBT technology, for 100-Gbit/s optical communication systems, are presented. We show how the appropriate implementation of the distributed amplifier concept in a bipolar transistors technology with high swing-speed product has enabled the realisation of an electro-optic modulator driver with 6.2- and 5.9-Vpp differential driving amplitude at 100 and 112 Gb/s, respectively, with a high signal quality. This circuit thus establishes the swing-speed product record at 660 Gb/s.V on wafer and at 575 Gb/s.V in a microwave module. In the frame of the European project POLYSYS, it has been co-packaged with a tunable laser and a modulator to realise a compact optoelectronic transmitter module, which has demonstrated performances advancing the state of the art of short reach 100-Gb/s optical communications.

This paper presents an overview of the research work currently being performed within the frame of project DAAB and its successor DAAB-TX towards the integration of ultra-wideband transceivers operating at mm-wave frequencies and capable of data rates up to 100 Gbits–¹. Two basic systemarchitectures are being considered: integrating a broadband antenna with a distributed amplifier and integrate antennas centered at adjacent frequencies with broadband active combiners or dividers. The paper discusses in detail the design of such systems and their components, fromthe distributed amplifiers and combiners, to the broadband silicon antennas and their single-chip integration. All components are designed for fabrication in a commercially available SiGe:C BiCMOS technology. The presented results represent the state of the art in their respective areas: 170 GHz is the highest reported bandwidth for distributed amplifiers integrated in Silicon; 89 GHz is the widest reported bandwidth for integrated-system antennas; the simulated performance of the two antenna integrated receiver spans 105 GHz centered at 148GHz, which would improve the state of the art by a factor in excess of 4 even against III-V implementations, if confirmed by measurements.

A high-precision mixed-signal mismatch measurement technique for metal-oxide metal (MoM) capacitors as well as the design of a 13-GHz 5-bit 360-degree phase shifter are presented. This thesis presents a high-precision, mixed-signal mismatch measurement technique for metal-oxide–metal capacitors. The proposed technique incorporates a switched-capacitor op amp within the measurement circuit to significantly improve the measurement precision while relaxing the resolution requirement on the backend analog-to-digital converter (ADC). The proposed technique is also robust against multiple types of errors. A detailed analysis is presented to quantify the sensitivity improvement of the proposed technique over the conventional one. In addition, this thesis proposes a multiplexing technique to measure a large number of capacitors in a single chip and a new layout to improve matching. A prototype fabricated in 180 nm CMOS technology demonstrates the ability to sense capacitor mismatch standard deviation as low as 0.045% with excellent repeatability, all without the need of a high-resolution ADC. The 13-GHz 5-bit 360-degree phase shifter consists of 2 stages. The first stage utilizes a delay line for 4-bit 180-degree phase shift. A second stage provides 1-bit 180-degree phase shift. The phase shifter includes gain tuning so as to allow a gain variation of less than 1 dB. The design has been fabricated in 180 nm CMOS technology and measurement results show a complete 360◦ phase shift with an average step size of 10.7◦ at 13-GHz. After calibration the phase shifter presented an output gain S21 of 0.5 dB with a gain variation of less than 1 dB across all codes at 13-GHz. The remaining s-parameter testing showed a S22 and S11 below -11 dB and a S12 below -49 dB at 13 GHz.