Conventional hydrological compartmental models have been shown to exhibit a high degree of uncertainty for predictions of peak flows, such as the design floods for design of hydropower infrastructure. One reason for these uncertainties is that conventional models are parameterised using statistical methods based on how catchments have responded in the past. Because the rare occurrence of peak flows, these are underrepresented during the periods used for calibration. This implies that the model has to be extrapolated beyond the discharge intervals where it has been calibrated. In this thesis, hydromechanical approaches are used to investigate the properties of stream networks, reflecting mechanisms including stage dependency, damming effects, interactions between tributaries (network effects) and the topography of the stream network. Further, it is investigated how these properties can be incorporated into the streamflow response functions of compartmental hydrological models. The response of the stream network was shown to vary strongly with stage in a non-linear manner, an effect that is commonly not accounted for in model formulation. The non-linearity is particularly linked to the flooding of stream channels and interactions with the flow on flood-plains. An evaluation of the significance of using physically based response functions on discharge predictions in a few sub-catchments in Southern Sweden show improvements (compared to a conventional model) in discharge predictions – particularly when modelling peak discharges. An additional benefit of replacing statistical parameterisation methods with physical parameterisation methods is the possibility of hydrological modelling during non-stationary conditions, such as the ongoing climate change. / QC 20101022

Network on Chip (NoC) has emerged as a competitive and efficient communication infrastructure for the core based design of System on Chip. Resource (core), router and interface between router and core are the three main parts of a NoC. Each core communicates with the network through the interface, also called Resource Network Interface (RNI). One approach to speed up the design at NoC based systems is to develop standardized RNI. Design of RNI depends to some extent on the type of routing technique used in NoC. Control of route decision base the categorization of source and distributed routing algorithms. In source routing a complete path to the destination is provided in the packet header at the source, whereas in distributed routing, the path is dynamically computed in routers as the packet moves through the network. Buffering, flitization, deflitization and transfer of data from core to router and vice versa, are common responsibilities of RNI in both types of routing. In source routing, RNI has an extra functionality of storing complete paths to all destinations in tables, extracting path to reach a desired destination and adding it in the header flit. In this thesis, we have made an effort towards designing and prototyping a standardized and efficient RNI for both source and distributed routing. VHDL is used as a design language and prototyping of both types RNI has been carried out on Altera DE2 FPGA board. Testing of RNI was conducted by using Nios II soft core. Simulation results show that the best case flit latency, for both types RNI is 4 clock cycles. RNI design is also resource efficient because it consumes only 2% of the available resources on the target platform.

The routing strategy used in today's Internet is best-effort service, where all data packets are treated equally. This type of service is not suited for applications such as video conferencing, and video on demand, that requires the availability of certain resources (such as bandwidth) to be guaranteed for them to function properly. The routing in this context, called Quality-of-Service (QoS) Routing, is the problem of finding suitable paths that meet the application's resource requirements. The majority of proposed QoS routing schemes operate by maintaining the global state of the network, and using this knowledge to compute the QoS route. However, all these schemes suffer from the inherent drawback of scalability, because of the need for each node to collect state information about the complete network. The other type of QoS routing schemes do not maintain network state information, but instead flood the network with QoS connection establishment requests. This type of scheme suffers from excessive message overhead during QoS connection establishment. In this thesis, we present a new QoS routing algorithm that is a combination of the above-mentioned two schemes (i.e., global state and flooding based). The algorithm aims at minimizing the message overhead associated with these two schemes and still maintaining the positive aspects of both of them. The basic idea of the algorithm is: to reach to a destination, the path(s) will always pass through a specific set of intermediate nodes. The algorithm discovers such intermediate nodes (limited by a hop count threshold value needed to reach there). When a QoS connection request arrives at a node, it selects the feasible path leading to the intermediate node for the requested destination. The QoS connection establishment message (or routing message) is forwarded along this path. When the message arrives at the intermediate node, the further path is decided through same logic. To decide the path that leads to the intermediate node, the algorithm maintains the link state related to these intermediate nodes, and link state updates are restricted only with regard to these intermediate nodes. Because of this restriction in link state updation, one has less message overhead, compared to the global state based routing scheme. Further, the algorithm tries to group these intermediate nodes in such a way that the routing message need be sent to only one of the grouped intermediate nodes, and still makes sure that all the possible paths are covered. Therefore, one has a reduced message overhead because of grouping.

<p>Network on Chip (NoC) has emerged as a competitive and efficient communication infrastructure for the core based design of System on Chip. Resource (core), router and interface between router and core are the three main parts of a NoC. Each core communicates with the network through the interface, also called Resource Network Interface (RNI). One approach to speed up the design at NoC based systems is to develop standardized RNI. Design of RNI depends to some extent on the type of routing technique used in NoC. Control of route decision base the categorization of source and distributed routing algorithms. In source routing a complete path to the destination is provided in the packet header at the source, whereas in distributed routing, the path is dynamically computed in routers as the packet moves through the network. Buffering, flitization, deflitization and transfer of data from core to router and vice versa, are common responsibilities of RNI in both types of routing. In source routing, RNI has an extra functionality of storing complete paths to all destinations in tables, extracting path to reach a desired destination and adding it in the header flit. In this thesis, we have made an effort towards designing and prototyping a standardized and efficient RNI for both source and distributed routing. VHDL is used as a design language and prototyping of both types RNI has been carried out on Altera DE2 FPGA board. Testing of RNI was conducted by using Nios II soft core. Simulation results show that the best case flit latency, for both types RNI is 4 clock cycles. RNI design is also resource efficient because it consumes only 2% of the available resources on the target platform.</p>

Given a geometric graph G = (V,E), where V is the set of vertices and E is the set of edges and a source-target pair {s,t} is a subset of V, a local geometric routing algorithm seeks a route from s to t using only local neighborhood relationships. This thesis proposes a local geometric routing algorithm that uses only a single state bit as message overhead and guarantees delivery of messages in three different classes of edge-augmented planar graphs: convex subdivisions, quasi planar convex subdivisions (allow some augmented edges on a spanning convex subdivision) and 2-augmented triangulations (allow some augmented edges on a spanning triangulation). The proposed algorithm is origin oblivious (does not require the knowledge of the origin vertex s) and predecessor oblivious (does not require the knowledge of the predecessor vertex).

Given a geometric graph G = (V,E), where V is the set of vertices and E is the set of edges and a source-target pair {s,t} is a subset of V, a local geometric routing algorithm seeks a route from s to t using only local neighborhood relationships. This thesis proposes a local geometric routing algorithm that uses only a single state bit as message overhead and guarantees delivery of messages in three different classes of edge-augmented planar graphs: convex subdivisions, quasi planar convex subdivisions (allow some augmented edges on a spanning convex subdivision) and 2-augmented triangulations (allow some augmented edges on a spanning triangulation). The proposed algorithm is origin oblivious (does not require the knowledge of the origin vertex s) and predecessor oblivious (does not require the knowledge of the predecessor vertex).

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<p>Network on Chip is a scalable and flexible communication infrastructure for the design of core based System on Chip. Communication performance of a NoC depends heavily on the routing algorithm. Deterministic and adaptive distributed routing algorithms have been advocated in all the current NoC architectural proposals. In this thesis we make a case for the use of source routing for NoCs, especially for regular topologies like mesh. The advantages of source routing include in-order packet delivery; faster and simpler router design; and possibility of mixing non-minimal paths in a mainly minimal routing. We propose a method to compute paths for various communications in such a way that traffic congestion is avoided while ensuring deadlock free routing. We also propose an efficient scheme to encode the paths.</p><p>We developed a tool in Matlab that computes paths for source routing for both general and application specific communications. Depending upon the type of traffic, this tool computes paths for source routing by selecting best routing algorithm out of many routing algorithms. The tool uses a constructive path improvement algorithm to compute paths that give more uniform link load distribution. It also generates different types of traffics. We also developed a simulator capable of simulating source routing for mesh topology NoC. The experiments and simulations which we performed were successful and the results show that the advantages of source routing especially lower packet latency more than compensate its disadvantages. The results also demonstrate that source routing can be a good routing candidate for practical core based SoCs design using network on chip communication infrastructure.</p>

Network on Chip is a scalable and flexible communication infrastructure for the design of core based System on Chip. Communication performance of a NoC depends heavily on the routing algorithm. Deterministic and adaptive distributed routing algorithms have been advocated in all the current NoC architectural proposals. In this thesis we make a case for the use of source routing for NoCs, especially for regular topologies like mesh. The advantages of source routing include in-order packet delivery; faster and simpler router design; and possibility of mixing non-minimal paths in a mainly minimal routing. We propose a method to compute paths for various communications in such a way that traffic congestion is avoided while ensuring deadlock free routing. We also propose an efficient scheme to encode the paths. We developed a tool in Matlab that computes paths for source routing for both general and application specific communications. Depending upon the type of traffic, this tool computes paths for source routing by selecting best routing algorithm out of many routing algorithms. The tool uses a constructive path improvement algorithm to compute paths that give more uniform link load distribution. It also generates different types of traffics. We also developed a simulator capable of simulating source routing for mesh topology NoC. The experiments and simulations which we performed were successful and the results show that the advantages of source routing especially lower packet latency more than compensate its disadvantages. The results also demonstrate that source routing can be a good routing candidate for practical core based SoCs design using network on chip communication infrastructure.