This thesis investigates in detail a multilevel cascaded STATCOM employing indirect voltage control and square-wave control in combination as control strategy. An analytical steady-state model of a multilevel converter in harmonic domain is developed that can be used, for example, for resonance studies within a multilevel converter, or/and in studying interactions between a multilevel STATCOM and the host ac grid (like harmonic resonance). A systematic method is developed for STATCOM system design and optimization of STATCOM system parameters. The focus lies on minimizing losses, minimizing voltage. Total Harmonic Distortion (THD) and minimizing dc voltage ripple. Analytical formulae are presented that can be used to calculate the best value of each STATCOM system parameters. A discrete and an analytical dynamic converter model of a multilevel converter are developed to enable dynamic and/or stability studies. For the discrete model, the operating modes of a single-cell are analysed in detail and emulated using signal generators and integrators. The analytical multilevel converter model is segmented into a dynamic and static part in order to represent accurately all internal feedback connections. A general approach is developed for dynamic modelling of a STATCOM system. The dynamic system model has modular structure, and the controller gains are selected by analyzing the root locus of the analytical model to give optimum responses. The model is very accurate in the sub-synchronous range, and it is adequate for most control design applications and practical stability issues below 100 Hz. The controller robustness is also studied where the analytical STATCOM system model is used to perform eigenvalue analysis and to design controllers. Two different advanced control techniques are investigated and compared against the conventional method of proportional integral (PI) feedback voltage control.

M.Ing. / The drive for smaller and higher density power supplies have been realised by advances in switching technologies, higher frequencies and smaller components. Along with the advances of higher switching frequencies, came a number of restrictive parasitic effects that were insignificant at lower frequencies (in use a few years ago). A problem that is becoming of increasing concern, as the frequencies increase, rise times decrease and current levels increase, is the reactance of the parasitic inductance in voltage fed converter. This inductance is responsible for a multitude of limitations and problems in high frequency converters, with the most important being unstable voltage supplies, large voltage spikes during switching (which leads to electromagnetic interference), and power transfer limitations. The main contributors of this parasitic inductance was found to be the inherent inductance of the conductors of the DC bus, the internal inductance of the capacitor elements used in the DC bus and the paralleling of these capacitor elements (capacitor bank). It was decided to investigate the cause of these identified inductances in an attempt at finding a means to reduce them, thereby improving the performance of the converter. This was accompanied by a search into prediction methods for the inductance and capacitance of the DC bus conductors. The ability to predict the inductance and capacitance inherent to the DC bus conductors, will allow for a large decrease in prototyping, and should give insight into the causes of these elements and how to manipulate them. This was done for the DC bus conductors, and led to insight into their inductance and capacitance origins. Means to reduce this inductance was found, along with the ability to predict the inductance and capacitance of a number of DC bus conductors. The last two identified parasitic inductance sources, the internal inductance of the capacitors and inductance of the capacitor bank, were then investigated. The cause of the inductance in the capacitor elements was discovered, along with the factors on which the capacitor elements are dependent. A great deal of the inductance, and its associated effects, can be avoided through proper capacitor selection and correct capacitor bank design. In order to bring this study in context with a practical scenario, the information previously obtained was incorporated in a full bridge voltage fed converter. The previous findings on inductance and capacitance held equally well when applied to a practical scenario. Additional means to reduce the effects of the parasitic inductances were discovered, and the inductance and capacitance prediction methods proved to be relatively accurate when applied to the DC bus conductors of a physical converter.

Thesis is submitted in fulfilment of the requirements for the degree of Master of Science in Engineering to the Faculty of Engineering and Built Environment, University of the Witwatersrand, Johannesburg 2018 / Power electronic converters that convert DC to AC, or vice versa, require an energy buffer between the AC and DC ports of the converter to compensate for the instantaneous power mismatch. Electrolytic capacitors are mostly used for these buffering applications because of the high energy density when compared to other capacitors, but unfortunately this type of capacitor also has low reliability. This dissertation proposes a general solution from a fundamental approach to solve the required capacitor power requirements on the DC-bus of an inverter. From the resulting model, an alternative active filter design technique to reduce the required capacitance of the DC-bus capacitor of a single phase inverter is presented. In this model, the minimum and maximum voltages of the capacitor can be chosen and the corresponding waveforms are calculated. An optimum region for the choice of capacitor voltage is shown to visually illustrate the trade-offs between the capacitor voltage, capacitance and converter losses. In this optimum area the reduction in capacitance is enough to allow the elimination of electrolytic capacitors, while maintaining comparable volume. In this technique, the DC-bus capacitor is decoupled from the DC-bus to allow wide voltage variation and the power processed by the capacitor is directly controlled, instead of the bus voltage. The allowable voltage variation of the capacitor can also be selected to fit the application or traded off in favour of capacitance as chosen by the designer. This general solution is applicable to any bi-directional converter used to decouple the capacitor from the DC-Bus / XL2018

Thesis (M.S.)--California Polytechnic State University, 2009. / Mode of access: Internet. Title from PDF title page; viewed on Jan. 6, 2010. Major professor: Taufik. "Presented to the faculty of California Polytechnic State University, San Luis Obispo." "In partial fulfillment of the requirements for the degree [of] Master of Science in Electrical Engineering." "December 2009." Includes bibliographical references (p. 74).

Thesis (Ph. D.)--University of Hong Kong, 1988.

Thesis (M. Phil.)--University of Hong Kong, 1973. / Mimeographed.

Thesis--M. Phil., University of Hong Kong.

Thesis (Ph. D.)--University of Hong Kong, 1988. / Xeroc copy of typescript. Also availalbe in microfilm.

Thesis--M. Phil., University of Hong Kong, 1979. / Photocopy of typewritten.

published_or_final_version / abstract / toc / Electrical and Electronic Engineering / Master / Master of Philosophy