A novel method for on-chip noise characterization of mm-wave circuits is presented. Different available methods for noise measurements and requirements for on-chip noise mea-surements are studied. The Y-factor method is chosen to be the more suitable method for in-situ applications since it does not require absolute measurements. A state of the art CMOS noise source is implemented in 32nm SOI CMOS technology to enable the in-situ noise measurements of a 20-35 GHz reconfigurable low noise amplifier. Measurement results show that the ENR of the noise source is repeatable enough so that the calibration of the noise source is only required for one integrated circuit. Using different scenarios for the noise figure response of the LNA, the performance of the noise source is evaluated. To the authors’ knowledge, this is the first time that an on-chip CMOS noise source is used for in-situ noise characterization of mm-wave frequency circuits.

An investigation into the stability of negative resistance-based source combining power amplifiers is conducted in this thesis. Two different negative resistance-based source combining topologies, a series and parallel version, are considered. Stability is analyzed using a simple and intuitive broadband approach that leverages linear circuit stability criterion and two different linearization methods: linearization around the operating point and in the frequency domain. Using this strategy, it is shown that conditions for self-sustained oscillation exist for both topologies. For the series combining topology, self-sustained oscillation is prevented by means of injection locking.

With an expected lifetime of 20 years and an expected cost of $500, the Cal Poly Sustainable Power for Electrical Resources (SuPER) project needed a strong central design. This thesis looks at the work completed by students over the previous 5 years, with an eye on the future, to create the phase 2 design. Part of this new structure focuses on a distributed communication bus for monitoring system health and status. Instead of complex and costly computer or FPGA systems, the new system will run solely with microcontrollers. This reduces costs and will hopefully still be used within 5, 10, and 20 years as the number of embedded devices continues to grow globally. The new system design was created using many systems engineering tools and benchmarks, including: requirements breakdown, hardware interfacing, software interfacing, safety, reliability, maintainability, and cost. Major components have been broken down into subsystems with well-defined requirements for implementation. These smaller projects can be completed by future team members as senior projects, independent work, or even Master’s theses. Upon test and integration, these subsystems will come together into a field-ready model to help bring power to the two billion people on Earth lacking it.

Distance education has the ability to transcend distance and time, reaching students anywhere at any time, particularly those underrepresented in engineering. Engineering is a practice-oriented profession requiring an interweaving of scientific theory and applied hands-on activities. Despite the need for distance education in engineering, few studies have systematically investigated the impact of student achievement and attitude in distance engineering laboratories. This quasi-experimental research addressed that need by studying the cognitive and affective domains of achievement in engineering laboratories while employing computer-based and traditional oscilloscopes. The students from two courses, electrical engineering for nonmajors and electronic fundamentals, were randomly assigned into treatment and comparison groups. The students' achievement and attitudes were gauged using assessment instruments and an attitudinal survey. These results were statistically analyzed and conclusions are discussed. The results suggested that computer-based instruments were viable in engineering laboratories.

Constraint satisfaction and optimization techniques are commonly employed in scheduling problems, industrial manufacturing, and automation processes. Constraint Satisfaction Problem (CSP) also finds use in the design, synthesis, and optimization of embedded systems. In recent years online constraint solving techniques have been employed in embedded systems for dynamic system adaptation. In embedded systems, online constraint solving techniques are primarily used as on-board control software. Using CSP techniques for scheduling algorithms provides intelligent scheduling. This thesis discusses the architecture of an embedded, parallel finite-domain constraint solver for performing online constraint satisfaction. By modeling the scheduling problem as a CSP problem, the embedded system becomes adaptable to dynamic changes in the environment. The features of this solver are that it is implemented in a platform with multiple soft-core processors with distributed memory architecture. A tool is also developed that automates the partitioning of the given application and configures the underlying framework.

As modern communication system technology develops, the demand for devices with smaller size, higher efficiency, and more functionality has increased dramatically. In addition, highly integrated RF-front-end modules with a reduced footprint and less transition loss between cascaded devices are desirable in most advanced wireless communication systems. Antenna arrays are widely used in wireless communication systems due to their high directivity and beam steering capability. Moreover, antenna arrays are preferred in mobile communication systems for diversity reception to reduce signal fading effects. In order to meet the various requirements of rapidly developing wireless communication systems, low cost, compact, multifunctional integrated antenna arrays are in high demand. Reconfigurable antennas that can flexibly adapt to different applications by dynamically changing their frequency and radiation properties have attracted a lot of attention. Frequency, radiation pattern, polarization, or a combination of two or more of these parameters in the reconfiguration of antennas was studied and presented in recent years. A single reconfigurable antenna is able to replace multiple traditional antennas and accomplish different tasks. Thus, the complexity of wireless communication systems can be greatly reduced with a smaller device size. On the other hand, the integration of antennas with other devices in wireless communication systems that can improve the efficiency and shrink the device size is a growing trend in antenna technology. Compact and highly efficient integrated filters and antennas were studied previously; the studies show that by seamlessly co-designing filters with patch antennas, the fractional bandwidth (FBW) of the antennas can be enhanced as compared to stand-alone antennas. However, the advantages of both the reconfigurable antenna and integrated filter/antenna technology have not been fully applied to antenna array applications. Therefore, this dissertation explores how to maximize the antenna array performance using reconfigurable antennas and integrated filter/antennas. A continuously frequency reconfigurable slot-ring antenna/array with switches and varactors is presented first. By changing the state of the loaded switches, the reconfigurable slot-ring antenna/array is able to operate as an L-band slot-ring antenna or a 2x2 S-band slot-ring antenna array. In each frequency band, the operation frequency of the antenna/array can be continuously tuned with the loaded varactors. To further enhance the functionality of the reconfigurable slot-ring antenna array, a dual-polarized fractal-shaped reconfigurable slot-ring antenna/array is developed with a reduced number of switches and an increased FBW. Additionally, ground plane solutions are explored to achieve single-sided radiation. The benefits of filter/antenna integration are also investigated in both linearly polarized patch phased arrays and circularly polarized patch antenna arrays. Finally, a preliminary study of a tunable integrated evanescent mode filter/antenna is conducted to validate the concept of combining reconfigurable antennas and integrated filter/antennas.

The benefit of the super-junction (SJ) technique and the use of a floating P layer for low voltage (30 V) laterally double-diffused metal oxide semiconductor (LDMOS) transistors are investigated in this thesis using Sentaurus TCAD simulation software. Optimizations to the SJ LDMOS were attempted such as adding a buffer layer to the device, but simulation and theoretical evidence point out that the benefits of the SJ technique are marginal at the 30 V application. A replacement for the SJ technique was sought, the floating P structure proved to be a good solution at the low voltage range due to its simpler cost effective process and performance gains achieved with optimization. A new idea of combining the floating P layer with shallow trench isolation is simulated yielding a low figure of merit (on state resistance x gate charge) of 5.93 mΩ-nC.

With the ever-increasing demand for low power electronics, neuromorphic computing has garnered huge interest in recent times. Implementing neuromorphic computing in hardware will be a severe boost for applications involving complex processes such as pattern recognition. Artificial neurons form a critical part in neuromorphic circuits, and have been realized with complex complementary metal–oxide–semiconductor (CMOS) circuitry in the past. Recently, insulator-to-metal-transition (IMT) materials have been used to realize artificial neurons. Although memristors have been implemented to realize synaptic behavior, not much work has been reported regarding the neuronal response achieved with these devices. In this work, we study the IMT in 1T-TaS2 and the volatile threshold switching behavior in vertical-MoS2 (v-MoS2) and graphene van der Waals heterojunction system. The v-MoS2/graphene threshold switching memristor (TSM) is used to produce the integrate-and-fire response of a neuron. We use large area chemical vapor deposited (CVD) graphene and MoS2, enabling large scale realization of these devices. These devices can emulate the most vital properties of a neuron, including the all or nothing spiking, the threshold driven spiking of the action potential, the post-firing refractory period of a neuron and strength modulated frequency response. These results show that the developed artificial neuron can play a crucial role in neuromorphic computing.

Two-dimensional materials provide a versatile platform for various electronic and optoelectronic devices, due to their uniform thickness and pristine surfaces. We probe the superior quality of 2D/2D and 2D/3D interfaces by fabricating molybdenum disulfide (MoS2)-based field effect transistors having hexagonal boron nitride (h-BN) and Al2O3 as the top gate dielectrics. An extremely low trap density of ~7x10^10 states/cm2-eV is extracted at the 2D/2D interfaces with h-BN as the top gate dielectric on the MoS2 channel. 2D/3D interfaces with Al2O3 as the top gate dielectric and SiOx as the nucleation layer exhibit trap densities between 7x10^10 and 10^11 states/cm2-eV, which is lower than previously reported 2D-channel/high-k-dielectric interface trap densities. The comparable values of trap time constants for both interfaces imply that similar types of defects contribute to the interface traps. This work establishes the case for van der Waals systems where the superior quality of 2D/2D and 2D/high-k dielectric interfaces can produce high performance electronic and optoelectronic devices.

The human face is frequently used as the biometric signal presented to a machine for identification purposes. Several challenges are encountered while designing face identification systems. The challenges are either caused by the process of capturing the face image itself, or occur while processing the face poses. Since the face image not only contains the face, this adds to the data dimensionality, and thus degrades the performance of the recognition system. Face Recognition (FR) has been a major signal processing topic of interest in the last few decades. Most common applications of the FR include, forensics, access authorization to facilities, or simply unlocking of a smart phone. The three factors governing the performance of a FR system are: the storage requirements, the computational complexity, and the recognition accuracy. The typical FR system consists of the following main modules in each of the Training and Testing phases: Preprocessing, Feature Extraction, and Classification. The ORL, YALE, FERET, FEI, Cropped AR, and Georgia Tech datasets are used to evaluate the performance of the proposed systems. The proposed systems are categorized into Single-Transform and Two-Transform systems. In the first category, the features are extracted from a single domain, that of the Two-Dimensional Discrete Cosine Transform (2D DCT). In the latter category, the Two-Dimensional Discrete Wavelet Transform (2D DWT) coefficients are combined with those of the 2D DCT to form one feature vector. The feature vectors are either used directly or further processed to obtain the persons' final models. The Principle Component Analysis (PCA), the Sparse Representation, Vector Quantization (VQ) are employed as a second step in the Feature Extraction Module. Additionally, a technique is proposed in which the feature vector is composed of appropriately selected 2D DCT and 2D DWT coefficients based on a residual minimization algorithm.