Cross-eye jamming is an Electronic Attack (EA) technique that induces an angular error in the radar being jammed. The main benefit of cross-eye jamming is that it is effective against monopulse tracking radars, which are largely immune to other forms of jamming. The objective of this research is to gain a complete understanding of cross-eye jamming so that systems that might be developed in future can be properly specied. The main contribution of this work is a comprehensive mathematical and experimental study of retrodirective cross-eye jamming. The mathematical analysis considers all aspects of an isolated, single-loop, retrodirective cross-eye jamming engagement, thereby avoiding the approximations inherent in other cross-eye jamming analyses. Laboratory experiments that accurately represent reality by using the radar for both transmission and reception, and simulating a true retrodirective cross-eye jammer were performed to validate the theoretical analysis. Lastly, the relationship between the angular error induced in the radar being jammed and the matching required from a cross-eye jammer system is explored. The most important conclusion of this work is that the traditional analyses of cross- eye jamming are inaccurate for the conditions under which cross-eye jammers operate. These inaccuracies mean that the traditional analyses are overly conservative, particularly at short ranges and for high cross-eye gains, suggesting that practical cross-eye jammers can be realised more easily than is generally believed. / Thesis (PhD)--University of Pretoria, 2010. / Electrical, Electronic and Computer Engineering / unrestricted

Approved for public release, distribution is unlimited / This thesis discusses VHDL modeling and simulation of a full custom Application Specific Integrated Circuit (ASIC) for a Digital Image Synthesizer (DIS). The DIS synthesizes the characteristic echo signature of a pre-selected target. It is mainly used against Inverse Synthetic Aperture Radars as an electronic counter measure. The VHDL description of the DIS architecture was exported from Tanner S-Edit, modified, and simulated in Aldec Active HDLTM. Simulation results were compared with C++ and Matlab simulation results for verification. Main subcomponents, a single Range Bin Processor (RBP), a cascade of 4 RBP s and a cascade of 16 RBP s were tested and verified. The overhead control circuitry, including Self Test Circuitry and Phase Extractor, was tested separately. Finally overall DIS was tested and verified using the control circuitry and a cascade of 4 RBP s together, representing the actual 512 RBP s. As a result of this research, the majority of the DIS was functionally tested and verified. / First Lieutenant, Turkish Army