The purpose of this investigation is to examine synthesis for reconstruction of electrostatic lenses having an axial potential distribution four times continuously differentiable. The solution of the electrode and pole piece reconstruction is given. Spline functions are used to approximate a continuous function to fit a curve. The present method of synthesis is based on cubic spline functions, which have only two simultaneous continuous derivatives, and all the other higher derivatives are ignored. The fifth-order or quintic spline is introduced simply because it has four simultaneous continuous derivatives. So the reconstruction program would have three terms appearing in the series expansion of the off-axis potential distribution, with regard to two terms when using cubic functions.

No description available.

No description available.

This study concerned the effects of short-term exposures to continuous (10 kv/meter) and pulsed 20 volts at 640 cps/100 msecs) electrostatic fields on the EEG recorded from external electrodes and hypothalamic activity recorded from implanted electrodes in rats. Each experiment lasted at least 90 minutes. The total energies of the waveforms recorded were integrated and printed out for plotting and analysis. Besides the brain activity, the ECG, respiration, and temperature of the animals were also monitored before, during,and after exposure to the electrostatic fields.

The purpose of this study had been to design and test a corona column and an insulating gas distribution system for a small tandem Van de Graaff. The intent of this paper is to describe the gas handling system and to compare experimentally the effects of corona electrode shape on the corona current carried between adjacent sections of the column.

The purpose of this study has been to construct two accelerating tubes with small beam apertures for the Van de Graaff, modifying the prototype tube designed and tested by Wiley (20), to design and construct a vacuum system for evacuating the tubes, and to determine the characteristics of the tube under operating conditions while installed in the generator.

In the past two decades much effort has been put in the characterization of the mechanical and surface properties at the nano-scale in order to conceive reliable N/MEMS (Nano and Micro ElectroMechanical Systems) applications. Techniques like nanoindentation, nanoscratching, atomic force microscopy have become widely used to measure the mechanical and surface properties of materials at sub-micro or nano scale. Nevertheless, many phenomena such us pile-up and pop-in as well as surface anomalies and roughness play an important role in the accurate determination of the materials properties. The first goal of this report is to study the infulence of these sources of data distortion on the experimental data. The results are discussed in the first experimental chapter. On the other hand, conceptors would like to adapt/tune the mechanical and surface properties as a function of the required application so as to adapt them to the industrial need. Coatings are usually applied to materials to enhance performances and reliability such as better hardness and elastic modulus, chemical resistance and wear resistance. In this work, the magnetron sputtering technique is used to deposit biocompatible thin layers of different compositions (titanium carbide, titanium nitride and amorphous carbon) over a titanium substrate. The goal of this second experimental part is the study of the deposition parameters influence on the resulting mechanical and surface properties. New materials such as nanocrystal superlattices have recently received considerable attention due to their versatile electronic and optical properties. However, this new class of material requires robust mechanical properties to be useful for technological applications. In the third and last experimental chapter, nanoindentation and atomic force microscopy are used to characterize the mechanical behavior of well ordered lead sulfide (PbS) nanocrystal superlattices. The goal of this last chapter is the understanding of the deformation process in order to conceive more reliable nanocrystal superlattices.

Microelectromechanical systems (MEMS) devices have been increasing in popularity for radio frequency (RF) and microwave communication systems due to the ability of MEMS devices to improve the performance of these circuits and systems. This interdisciplinary field combines the aspects of lithographic fabrication, mechanics, materials science, and RF/microwave circuit technology to produce moving structures with feature dimensions on the micron scale (micro structures). MEMS technology has been used to improve switches, varactors, and inductors to name a few specific examples. Most MEMS devices have been fabricated using planar micro fabrication techniques that are similar to current IC fabrication techniques. These techniques limit the thickness of individual layers to a few microns, and restrict the structures to have planar and not vertical features. <p> One micro fabrication technology that has not seen much application to microwave MEMS devices is LIGA, a German acronym for X-ray lithography, electroforming, and moulding. LIGA uses X-ray lithography to produce very tall structures (hundreds of microns) with excellent structural quality, and with lateral feature sizes smaller than a micron. These unique properties have led to an increased interest in LIGA for the development of high performance microwave devices, particularily as operating frequencies increase and physical device size decreases. Existing work using LIGA for microwave devices has concentrated on statically operating structures such as transmission lines, filters, and couplers. This research uses these unique fabrication capabilities to develop dynamically operating microwave devices with high frequency performance. <p>This thesis documents the design, simulation, fabrication, and testing of MEMS variable capacitors (varactors), that are suitable for fabrication using the LIGA process. Variable capacitors can be found in systems such as voltage-controlled oscillators, filters, impedance matching networks and phase shifters. Important figures-of-merit for these devices include quality factor (Q), tuning range, and self-resonant frequency. The simulation results suggest that LIGA-MEMS variable capacitors are capable of high Q performance at upper microwave frequencies. Q-factors as large as 356 with a nickel device layer and 635 with a copper device layer, at operational frequency, have been simulated. The results indicate that self-resonant frequencies as large as 45 GHz are possible, with the ability to select the tuning range depending on the requirements of the application. Selected capacitors were fabricated with a shorter metal height for an initial fabrication attempt. Test results show a Q-factor of 175 and a nominal capacitance of 0.94 pF at 1 GHz. The devices could not be actuated as some seed layer metal remained beneath the cantilevers and further etching is required. As such, LIGA fabrication is shown to be a very promising technology for various dynamically operating microwave MEMS devices.

ESD, the discharge of electrostatically generated charges into an IC, is one of the most important reliability problems for ultra-scaled devices. This electrostatic charge can generate voltages of up to tens of kilovolts. These very high voltages can generate very high electric fields and currents across semiconductor devices, which may result in dielectric damage or melting of semiconductors and contacts. It has been reported that up to 70% of IC failures are caused by ESD. Therefore, it’s necessary to design a protection circuit for each pin that discharges the ESD energy to the ground. As the devices are continuously scaling down, while ESD energy remains the same, they become more vulnerable to ESD stress. This higher susceptibility to ESD damage is due to thinner gate oxides and shallower junctions. Furthermore, higher operating frequency of the scaled technologies enforces lower parasitic capacitance of the ESD protection circuits. As a result, increasing the robustness of the ESD protection circuits with minimum additional parasitic capacitance is the main challenge in state of the art CMOS processes. Providing a complete ESD immunity for any circuit involves the design of proper protection circuits for I/O pins in addition to an ESD clamp between power supply pins. In this research both of these aspects are investigated and optimized solutions for them are reported. As Silicon Controlled Rectifier (SCR) has the highest ESD protection level per unit area, ESD protection for I/O pins is provided by optimizing the first breakdown voltage and latch-up immunity of SCR family devices. The triggering voltage of SCR is reduced by a new implementation of gate-substrate triggering technique. Furthermore, a new device based on SCR with internal darlington pair is introduced that can provide ESD protection with very small parasitic capacitance. Besides reducing triggering voltage, latch-up immunity of SCR devices is improved using two novel techniques to increase the holding voltage and the holding current. ESD protection between power rails is provided with transient clamps in which the triggering circuit keeps the clamp “on” during the ESD event. In this research, two new clamps are reported that enhance the triggering circuit of the clamp. The first method uses a CMOS thyristor element to provide enough delay time while the second method uses a flip flop to latch the clamp into “on” state at the ESD event. Moreover, the stability of transient clamps is analyzed and it’s been shown that the two proposed clamps have the highest stability compared to other state of the art ESD clamps. Finally, in order to investigate the impact of ESD protection circuits on high speed applications a current mode logic (CML) driver is designed in 0.13μm CMOS technology. The protection for this driver is provided using both MOS-based and SCR-based protection methods. Measurement results show that, compared to MOS-based protection, SCR-based protection has less impact on the driver performance due to its lower parasitic capacitance.

ESD, the discharge of electrostatically generated charges into an IC, is one of the most important reliability problems for ultra-scaled devices. This electrostatic charge can generate voltages of up to tens of kilovolts. These very high voltages can generate very high electric fields and currents across semiconductor devices, which may result in dielectric damage or melting of semiconductors and contacts. It has been reported that up to 70% of IC failures are caused by ESD. Therefore, it’s necessary to design a protection circuit for each pin that discharges the ESD energy to the ground. As the devices are continuously scaling down, while ESD energy remains the same, they become more vulnerable to ESD stress. This higher susceptibility to ESD damage is due to thinner gate oxides and shallower junctions. Furthermore, higher operating frequency of the scaled technologies enforces lower parasitic capacitance of the ESD protection circuits. As a result, increasing the robustness of the ESD protection circuits with minimum additional parasitic capacitance is the main challenge in state of the art CMOS processes. Providing a complete ESD immunity for any circuit involves the design of proper protection circuits for I/O pins in addition to an ESD clamp between power supply pins. In this research both of these aspects are investigated and optimized solutions for them are reported. As Silicon Controlled Rectifier (SCR) has the highest ESD protection level per unit area, ESD protection for I/O pins is provided by optimizing the first breakdown voltage and latch-up immunity of SCR family devices. The triggering voltage of SCR is reduced by a new implementation of gate-substrate triggering technique. Furthermore, a new device based on SCR with internal darlington pair is introduced that can provide ESD protection with very small parasitic capacitance. Besides reducing triggering voltage, latch-up immunity of SCR devices is improved using two novel techniques to increase the holding voltage and the holding current. ESD protection between power rails is provided with transient clamps in which the triggering circuit keeps the clamp “on” during the ESD event. In this research, two new clamps are reported that enhance the triggering circuit of the clamp. The first method uses a CMOS thyristor element to provide enough delay time while the second method uses a flip flop to latch the clamp into “on” state at the ESD event. Moreover, the stability of transient clamps is analyzed and it’s been shown that the two proposed clamps have the highest stability compared to other state of the art ESD clamps. Finally, in order to investigate the impact of ESD protection circuits on high speed applications a current mode logic (CML) driver is designed in 0.13μm CMOS technology. The protection for this driver is provided using both MOS-based and SCR-based protection methods. Measurement results show that, compared to MOS-based protection, SCR-based protection has less impact on the driver performance due to its lower parasitic capacitance.