Sustainable Built Environments Senior Capstone / This case study examines housing on the Hopi reservation, both traditional and contemporary and aims to create a future type of housing that will contribute to addressing the critical housing needs and alternative solutions addressing substandard housing on and for the Hopi people. Westernization has created a plague of substandard housing on the reservation that ignores pre-existing vernacular architecture and thus, the environment and the culture of the Hopi people. Rather, Westernization has created a move toward inexpensive, and quick but highly inefficient types of housing. The housing situation on Hopi presents a critical need for solution, an alternative to the substandard housing by creating a housing design that is sustainable, affordable and energy efficient. This solution can be found by (re)linking to cultural patterns of sustainability, essentially the history of a cultural people which includes traditional housing methods and materials. Traditional Hopi housing was studied and a list of common strategies was compiled from traditional houses on the reservation into a Basecase. Modern strategies were applied to the Basecase to create a Newcase. The percent savings in annual energy use and annual operation costs were compared between the two cases, however, it is important to note that the results were skewed due to a variety of factors that are discussed as limitations in the study. Nevertheless, the study offered an alternative housing solution, one that demonstrated significant savings in annual energy use and operation costs.

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The Swedish government in the 1960th initiated “The Million Program” to build million residentialunits to cover the housing shortage between 1965 to 1975. Tjärna Ängar neighborhood in Borlängemunicipality was built during the million-program period, where these residential units became old,and the indoor environment is uncomfortable for the residents.Recently, there have been extensive energy-efficient renovations to improving the energyefficiency,indoor air quality, and thermal comfort of these buildings. The renovation project, withcooperation between Dalarna University and the local housing company (Stora Tunabyggen)started in 2015 by renovating three buildings in the Tjärna Ängar neighborhood.This study was conducted at one of these three retrofitting buildings (Kornstigen 25) to investigatethe thermal comfort in the building following energy retrofit. The assessment of the thermalcomfort in this study is based on Fanger's model with the use of predicted mean vote (PMV) andpredicted percentage of dissatisfied (PPD) to assess the obtained measurements.An online questionnaire survey with building occupants was conducted to give a betterunderstanding of the current situation of the retrofitting building before and after the renovationregarding thermal comfort. Based on the measurement, the thermal sensation of the occupants isslightly cool according to the standard’s sensation scale during the period of the measurement. Anonline questionnaire survey assures that the occupants were feeling slightly cool during someperiods of the day inside the apartments.

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Encouraging the uptake of energy efficient vehicles (EEVs) is an aspiration of critical importance in a day and age in which we are confronted with the increasingly dire consequences of human behaviour on our planet, and on the planet for generations to come. The transport sector is one of the highest contributors of anthropogenic greenhouse gas emissions, whilst pollution from this sector is responsible for a large proportion of human deaths each and every year. Given the severity of these issues, it is more important than ever for policy-makers, and researchers alike, to encourage a transition within the community towards more sustainable lifestyles. Transportation is key to this change. As a service that every human being uses, almost every day of his or her life, the transport sector presents a unique opportunity for behavioural change. Through efficient and targeted policies, consumers can be incentivised to make more sustainable transport choices and to consider the consequences of their own actions. Foremost amongst these initiatives is that of encouraging a transition towards energy efficient vehicles. This thesis has been produced in order to shed further light on issues affecting this transition. In particular for policy-makers, this document includes a series of recommendations based on prevailing findings in the current literature, in addition to the novel and significant findings of this research effort. These include the various lessons learnt from government policies that have already been implemented in regions around the globe. As a thesis by publication, this document consists of four research articles that investigate factors affecting the EEV market, specifically in terms of: consumer demand, vehicle usage and product pricing. A number of other demographic and economic factors have also been examined, including the role of economies-of-scale. / Att uppmuntra ökad användningen av energieffektiva fordon (EEVs) är en strävan av avgörande betydelse i en tid då vi konfronteras med de allt mer ödesdigra konsekvenserna av människors påverkan på vår planet, i dag och för kommande generationer. Transportsektorn är en av de sektorer som bidrar mest till utsläppen av antropogena växthusgaser. Utsläpp från transportsektorn bidrar även till ett stort antal dödsfall varje år. Med tanke på vikten av dessa frågor är det viktigare än någonsin för beslutsfattare och forskare att bidra till en samhällsövergång mot mer hållbara livsstilar. Transporter är avgörande i denna omvandling. Eftersom transporter är en tjänst som alla människor utnyttjar i stort sett varje dag, erbjuder transportsektorn en unik möjlighet till beteendeförändringar. Genom effektiva och målinriktade åtgärder kan konsumenter ges incitament att göra mer hållbara transportval och överväga konsekvenserna av sina handlingar. Främst bland dessa initiativ är en uppmuntran till en övergång mot mer energieffektiva fordon. Denna avhandling har tagits fram i syfte att belysa frågeställningar som berör denna övergång. För framför allt beslutsfattare innehåller avhandlingen en rad rekommendationer baserade på såväl rådande forskningsresultat från aktuell forskningslitteratur som nya resultat från denna forskningsinsats. Dessa inkluderar erfarenheter från redan implementerade politiska åtgärder från regioner runt om i världen. Denna sammanläggningsavhandling består av fyra forskningsartiklar som undersöker faktorer som påverkar EEV-marknaden vad gäller konsumentefterfrågan, fordonsanvändning och produktprissättning. Utöver dessa har även ett antal andra demografiska och ekonomiska faktorer, inklusive betydelsen av stordriftsfördelar, undersökts. / <p>QC 20160503</p>

Energy efficiency is of the utmost importance in modern high-performance embedded processor design. As the number of transistors on a chip continues to increase each year, and processor logic becomes ever more complex, the dynamic switching power cost of running such processors increases. The continual progression in fabrication processes brings a reduction in the feature size of the transistor structures on chips with each new technology generation. This reduction in size increases the significance of leakage power (a constant drain that is proportional to the number of transistors). Particularly in embedded devices, the proportion of an electronic product’s power budget accounted for by the CPU is significant (often as much as 50%). Dynamic branch prediction is a hardware mechanism used to forecast the direction, and target address, of branch instructions. This is essential to high performance pipelined and superscalar processors, where the direction and target of branches is not computed until several stages into the pipeline. Accurate branch prediction also acts to increase energy efficiency by reducing the amount of time spent executing mis-speculated instructions. ‘Stalling’ is no longer a sensible option when the significance of static power dissipation is considered. Dynamic branch prediction logic typically accounts for over 10% of a processor’s global power dissipation, making it an obvious target for energy optimisation. Previous approaches at increasing the energy efficiency of dynamic branch prediction logic has focused on either fully dynamic or fully static techniques. Dynamic techniques include the introduction of a new cache-like structure that can decide whether branch prediction logic should be accessed for a given branch, and static techniques tend to focus on scheduling around branch instructions so that a prediction is not needed (or the branch is removed completely). This dissertation explores a method of combining static techniques and profiling information with simple hardware support in order to reduce the number of accesses made to a branch predictor. The local delay region is used on unconditional absolute branches to avoid prediction, and, for most other branches, Adaptive Branch Bias Measurement (through profiling) is used to assign a static prediction that is as accurate as a dynamic prediction for that branch. This information is represented as two hint-bits in branch instructions, and then interpreted by simple hardware logic that bypasses both the lookup and update phases for appropriate branches. The global processor power saving that can be achieved by this Combined Algorithm is around 6% on the experimental architectures shown. These architectures are based upon real contemporary embedded architecture specifications. The introduction of the Combined Algorithm also significantly reduces the execution time of programs on Multiple Instruction Issue processors. This is attributed to the increase achieved in global prediction accuracy.

The primary obstacle to continued downscaling of charge-based electronic devices in accordance with Moore's law is the excessive energy dissipation that takes place in the device during switching of bits. Unlike charge-based devices, spin-based devices are switched by flipping spins without moving charge in space. Although some energy is still dissipated in flipping spins, it can be considerably less than the energy associated with current flow in charge-based devices. Unfortunately, this advantage will be squandered if the method adopted to switch the spin is so energy-inefficient that the energy dissipated in the switching circuit far exceeds the energy dissipated inside the system. Regrettably, this is often the case, e.g., switching spins with a magnetic field or with spin-transfer-torque mechanism. In this dissertation, it is shown theoretically that the magnetization of two-phase multiferroic single-domain nanomagnets can be switched very energy-efficiently, more so than any device currently extant, leading possibly to new magnetic logic and memory systems which might be an important contributor to Beyond-Moore's-Law technology. A multiferroic composite structure consists of a layer of piezoelectric material in intimate contact with a magnetostrictive layer. When a tiny voltage of few millivolts is applied across the structure, it generates strain in the piezoelectric layer and the strain is transferred to the magnetostrictive nanomagnet. This strain generates magnetostrictive anisotropy in the nanomagnet and thus rotates its direction of magnetization, resulting in magnetization reversal or 'bit-flip'. It is shown after detailed analysis that full 180 degree switching of magnetization can occur in the "symmetric" potential landscape of the magnetostrictive nanomagnet, even in the presence of room-temperature thermal fluctuations, which differs from the general perception on binary switching. With proper choice of materials, the energy dissipated in the bit-flip can be made as low as one attoJoule at room-temperature. Also, sub-nanosecond switching delay can be achieved so that the device is adequately fast for general-purpose computing. The above idea, explored in this dissertation, has the potential to produce an extremely low-power, yet high-density and high-speed, non-volatile magnetic logic and memory system. Such processors would be well suited for embedded applications, e.g., implantable medical devices that could run on energy harvested from the patient's body motion.

The thesis evaluates the viability of reducing power consumption of a contem- porary computer cluster by using more power-efficient hardware components. The cluster in question runs an Map-Reduce algorithm implementation and the worker nodes consist of either systems with an ARM CPU or systems which combine both an ARM CPU and an FPGA in a single package. The behavior of such cluster is discussed from both performance side as well as power consumption side. The text discusses the problems and peculiarities with the integration of an ARM-based and especially the combined ARM-FPGA-based systems into the Map-Reduce framework. The Map-Reduce framework performance itself is eval- uated to identify the gravest performance bottlenecks when using the framework in the environment with ARM systems. 1

Data streaming applications, such as signal processing, multimedia applications, often require high computing capacity, yet also have stringent power constraints, especially in portable devices. General purpose processors can no longer meet these requirements due to their sequential software execution. Although fixed logic ASICs are usually able to achieve the best performance and energy efficiency, ASIC solutions are expensive to design and their lack of flexibility makes them unable to accommodate functional changes or new system requirements. Reconfigurable systems have long been proposed to bridge the gap between the flexibility of software processors and performance of hardware circuits. Unfortunately, mainstream reconfigurable FPGA designs suffer from high cost of area, power consumption and speed due to the routing area overhead and timing penalty of their bit-level fine granularity. In this dissertation, we present an architecture design, application mapping and performance evaluation of a novel coarse-grained reconfigurable architecture, named SmartCell, for data streaming applications. The system tiles a large number of computing cell units in a 2D mesh structure, with four coarse-grained processing elements developed inside each cell to form a quad structure. Based on this structure, a hierarchical reconfigurable network is developed to provide flexible on-chip communication among computing resources: including fully connected crossbar, nearest neighbor connection and clustered mesh network. SmartCell can be configured to operate in various computing modes, including SIMD, MIMD and systolic array styles to fit for different application requirements. The coarse-grained SmartCell has the potential to improve the power and energy efficiency compared with fine-grained FPGAs. It is also able to provide high performance comparable to the fixed function ASICs through deep pipelining and large amount of computing parallelism. Dynamic reconfiguration is also addressed in this dissertation. To evaluate its performance, a set of benchmark applications has been successfully mapped onto the SmartCell system, ranging from signal processing, multimedia applications to scientific computing and data encryption. A 4 by 4 SmartCell prototype system was initially designed in CMOS standard cell ASIC with 130 nm process. The chip occupies 8.2 mm square and dissipates 1.6 mW/MHz under fully operation. The results show that the SmartCell can bridge the performance and flexibility gap between logic specific ASICs and reconfigurable FPGAs. SmartCell is also about 8% and 69% more energy efficient and achieves 4x and 2x throughput gains compared with Montium and RaPiD CGRAs. Based on our first SmartCell prototype experiences, an improved SmartCell-II architecture was developed, which includes distributed data memory, segmented instruction format and improved dynamic configuration schemes. A novel parallel FFT algorithm with balanced workloads and optimized data flow was also proposed and successfully mapped onto SmartCell-II for performance evaluations. A 4 by 4 SmartCell-II prototype was then synthesized into standard cell ASICs with 90 nm process. The results show that SmartCell-II consists of 2.0 million gates and is fully functional at up to 295 MHz with 3.1 mW/MHz power consumption. SmartCell-II is about 3.6 and 28.9 times more energy efficient than Xilinx FPGA and TI's high performance DSPs, respectively. It is concluded that the SmartCell is able to provide a promising solution to achieve high performance and energy efficiency for future data streaming applications.

This thesis focuses on the synthesis and characterisation of titanium dioxide (TiO2) thin films for photocatalytic applications and use in semi-transparent dye-sensitised solar cells for energy efficient glazing. Several synthetic methods for the production of TiO2 thin films are explored including sol-gel, aerosol-assisted chemical vapour deposition (CVD) and hybrid combinatorial CVD. For sol-gel processing two different precursors were studied; titanium tetra-isopropoxide (TTIP) and titanium bis-ammonium lactato dihydroxide (TiBALD). Non-ionic surfactants (Tween 20, 40, 60 and Brij 58 and 98) were successfully incorporated into all three methods for the production of TiO2 thin films modified morphology, microstructure and enhanced functional properties in some cases. All films are fully characterised using scanning electron microscopy, X-ray diffraction, atomic force microscopy, Raman spectroscopy, UV-Vis spectroscopy, contact angle analysis, as well as assessment for photocatalytic performance with resazurin 'intelligent' ink. Photocatalytic performance has been used as an indicator for performance in dye-sensitised solar cells (DSSCs). The best photocatalytic performances with half-lives of up to 2 minutes were obtained for thin films produced with the addition of Brij surfactants. A selection of thin films were tested in semi-transparent DSSC devices with up to 70% transparency, to determine their overall potential for use as energy-efficient glazing. Three DSSC device configurations were tested, whereby the optimum configuration used N3 "black" dye with a dye loading time of 42 hours in combination with a high performance iodine electrolyte and a platinum counter electrode. The highest power conversion efficiencies (PCE) obtained were within the region of 0.1 - 0.3 %, with the highest PCE of 0.3814 % obtained with a 3-layer TTIP sol-gel derived Brij 58 thin film (0.0006 mol dm3) which exhibited an short-circuit current of 0.857 mA/cm2, an open-circuit voltage of 0.71 V and a fill factor of 0.60.