Arithmetic units and logic circuits are critical components of any VLSI system. Thus realizing efficient arithmetic units and logic circuits is required for better performance of a data path unit and therefore microprocessor or digital signal processor (DSP). Adders are basic building blocks of any processor or data path application. For the design of high performance processing units, high-speed adders with low power consumption is a requirement. Carry Select Adder (CSA) is known to be one of the fastest adders used in many data processing applications. This first contribution of the dissertation is the design of a new CSA architecture using Manchester carry chain (MCC) in multioutput domino CMOS logic. It employs a novel MCC blocks in a hierarchical approach in the design of the CSA. The proposed MCC block is also extended in designing a power-delay and area efficient Vedic multiplier based on "Urdhva-Tiryakbhyam”. The simulation results shows that the proposed architecture achieves two fold advantages in terms of power-delay product (PDP) and hardware overhead. Apart from adders and multipliers, counters also play a major role in a data path unit. Counters are basic building blocks in many VLSI applications such as timers, memories, ADCs/DACs, frequency dividers etc. It is observed that design of counters has power overhead because of requirement of high power consumption for the clock signal distribution and undesired activity of flip-flops due to presence of clocks. The second contribution of the dissertation is the power efficient design of synchronous counters that reduces the power consumption due to clock distribution for different flip-flops and offers high reliability. The simulation results shows that the proposed counter design has lower power requirement and power-area product than existing counter architectures. Pipelines can be used for achieving high circuit operating speeds. However, as the operating frequency increases, the number of pipeline stages also increase linearly and so the memory elements. The third contribution of the dissertation is the dynamic memory-less pipeline design based on sinusoidal three-phase clocking scheme that reduces the power required by the clock and offers high circuit operating frequencies. Finally, the dissertation presents a novel tool for Boolean-function realization with minimum number of transistor in series. This tool is based on applying a new functional decomposition algorithms to decompose the initial Boolean-function into a network of smaller sub-functions and subsequently generating the final circuit. The effectiveness of proposed technique is estimated using circuit level simulations as well as using automated tool. The number of levels required using proposed technique is reduced by an average of 70% compared to existing techniques.

Energy efficiency is a key requirement for wireless sensor nodes, biomedical implants, and wearable devices. The energy consumption of the sensor node needs to be minimized to avoid battery replacement, or even better, to enable the device to survive on energy harvested from the ambient. Capacitive sensors do not consume static power; thus, they are attractive from an energy efficiency perspective. In addition, they can be employed in a wide range of sensing applications. However, the sensor readout circuit–i.e., the capacitance-to-digital converter (CDC)–can be the dominant source of energy consumption in the system. Thus, the development of energy-efficient CDCs is crucial to minimizing the energy consumption of capacitive sensor nodes. In the first part of this dissertation, we propose several energy-efficient CDC architectures for low-energy sensor nodes. First, we propose a digitally-controlled coarsefine multislope CDC that employs both current and frequency scaling to achieve significant improvement in energy efficiency. Second, we analyze the limitations of successive approximation (SAR) CDC, and we address these limitations by proposing a robust parasitic-insensitive opamp-based SAR CDC. Third, we propose an inverter-based SAR CDC that achieves an energy efficiency figure-of-merit (FoM) of 31fJ/Step, which is the best energy efficiency FoM reported to date. Fourth, we propose a differential SAR CDC with quasi-dynamic operation to maintain excellent energy efficiency for a scalable sample rate. In the second part of this dissertation, we study the matching properties of small integrated capacitors, which are an integral component of energy-efficient CDCs. Despite conventional wisdom, we experimentally illustrate that the mismatch of small capacitors can be directly measured, and we report mismatch measurements for subfemtofarad integrated capacitors. We also correct the common misconception that lateral capacitors match better than vertical capacitors, and we identify the conditions that make one implementation preferable. In the third and last part of this dissertation, we investigate the potential of novel metal-organic framework (MOF) thin films in capacitive gas sensing. We provide sensitivity-based optimization and simple fabrication flow for capacitive interdigitated electrodes. We use a custom flexible gas sensor test setup that is designed and built in-house to characterize MOF-based capacitive gas sensors.