Software emulation of local area and wide area networks provides an alternative method for the design of such networks and for analyzing their performance. Emulation of bridges and routers that link networks together may provide valuable information regarding network congestion, network storms and the like before putting expensive hardware into place. Such an emulation also enables students taking a networking course to develop their own client-server applications and to visualize the basic functioning of the UDP/IP and RIP protocols.This thesis builds on the emulated local area network, Metanet, created by a previous graduate student. It adds the capability of attaching routers and bridges to multiple local and non-local emulated networks so that data may be transferred between two hosts on different segments of the same LAN (via an emulated bridge) or two different networks altogether (via an emulated router). The machines running the Metanet software should support UNIX which has Berkeley's Socket interface as emulated networks on different physical machines utilize this interface for communicating. A comparison of the new networking capabilities of Metanet and other experimental systems like XINU and MINIX is researched. / Department of Computer Science

This research has shown that a knowledge-based system is an effective tool to help novice simulation users interpret and understand simulation output. The thesis describes the development and empirical evaluation of the prototype. A simulation program which adopts the discrete-event simulation approach simulates the behaviour of a local area network protocol, i.e., the Ethernet, with different sets of parameter values. The knowledge-based system carries out the 'analysis' of the simulation output covering the protocol efficiency and throughput. The knowledge-based system summarises the simulation output and upon request from the user, provides explanations to a conclusion arrived at. The summary is the relationship between any pair of variables; and the explanation is the justification as to how the pair are related. The strategy for building the knowledge base using production rules is also elaborated. There are different functions performed by the different sets of rules (or rule-sets). Their major functions, In parallel with the development objective, are interpreting numerical data, presenting output to users and providing explanations interactively. The rules are grouped accordingly to make the knowledge bases easier to maintain. In the explanation aspect, the few approaches attempted by other researchers to improve expert system explanation is discussed. It is argued that a mere regurgitation of 'fired' rules to explain the Ethernet behaviour is not adequate in this case. To circumvent this problem, a 'constructive' approach to explanation is employed. The explanation procedure rewrites the 'fired' rules in a more understandable form than the if-then rules. Unnecessary parts of the rules are ommitted to make the explanations clearer. Finally, an experiment carried out to evaluate the effectiveness of the prototype is described in detail. The effectiveness is measured from a few different perspectives. These are test scores, completion time for the test and the users' degree of confidence, both in the interpretation and explanation tasks. The results show that although some responses are mixed, there is evidence to suggest that the knowledge-based simulation system environment is beneficial to the target users.

Stuttgart, FH, Diplomarb., 2003.

Thesis (Ph. D.)--Lehigh University, 2005. / Includes vita. Includes bibliographical references (leaves 111-117).

Στην εργασία παρουσιάζεται η μελέτη, η πιστοποίηση και η εφαρμογή των μηχανισμών εκείνων που οδηγούν στην παροχή end-to-end QoS σε ενοποιημένα L2 και MPLS δίκτυα. / In a real IP network such as the Internet, the basic type of service offered is the best effort one. In the best effort service all packets are treated equally and there are no guarantees, variations or attempt to enforce justice. However, the network seeks to promote as much traffic as possible with “reasonable” quality. Network congestion is a frequent phenomenon that is introduced when a network device stores packets at the output queue as it receives more packets from those that it can transmit. During congestion packets suffer from delay and once the output queue becomes full, these packets are dropped. However, there are applications that require certain guarantees (especially regarding delay and packet drops) such as real-time data transmission applications (e.g. IP telephony, voice over IP) and videoconference. Quality guarantees for these applications can be ensured if they can cross empty or nearempty network queues. This can only be achieved through mechanisms that can ensure the capacity and availability of the network queues. A means to provide quality guarantees to certain types of traffic is the special management of certain packets compared to the other. At this point the term Quality of Service (QoS) is introduced. A definition for QoS is: "the ability of a network element to provide a level of guarantee to a subset of traffic that ensures that the requirements of the service can be achieved with a defined (high) probability". In reality, the mechanisms of QoS do not provide larger network capacity or something similar, but they rather provide better network management so that it can be used more effectively and it can meet and address the requirements of the applications. In recent years, efforts have focused on providing quality of service at the network layer (Layer 3) so that it can be also applied on the Internet. Using architectures such as IntServ and DiffServ it is now possible to provide quality service at the network layer. However, the requirement for end-to-end QoS along with the expansion of networks towards switching equipment, creates the need for the application of QoS in the next lower layer, that is the data link layer (Layer 2). Hence, it should be borne in mind that the interoperability between the network and data link layers will lead to the provision of a single, transparent level of QoS. Based on the above, it becomes clear that in order to achieve end-to-end QoS, apart from the need for extension of the QoS to the data link layer there is also the need and requirement of interoperability with existing implementations in the network layer. In this direction, this dissertation focuses on studying the application of QoS to the data link layer. Furthermore, given the provision of quality of service to the IP layer, this dissertation considers the integration of QoS provision at Layer 2 and Layer 3. Therefore, the objective of this dissertation is twofold: a) QoS provision over Layer2-Ethernet networks and b) QoS provision over Layer 2 VPNs. For the implementation of Layer 2 QoS over Ethernet networks the IEEE 802.1p standard has been proposed. This standard has 3 bits length and is part of Tag Control Information field. During this dissertation performance tests were carried out on switches sorting traffic under CoS, which results in 8 different classes of traffic. Furthermore, queue configuration techniques on switches have been studied along with the cases of per port/per 802 .1q priorities and traffic classification. For the implementation of L2 QoS over VPNs there are techniques that are strongly related to the VPN type. This dissertation presents cases that L2 MPLS VPNs are used for the provisioning of either point-to-point (EoMPLS) or point-tomultipoint (VPLS) VPNs. In addition, research has been carried out for the extension of QoS provision over L2 MPLS VPNs to end-points that is purely L2 domain. The analysis at L2 domain was realized with the IEEE 802.1 p standard. Furthermore, the ability to provide QoS over multipoint L2 VPNs has been studied. Initially, the focus was on L3 devices (routers) and it was then extended to L2 using IEEE 802.1 p. Thus, the overall implementation was based on the combined use of 802.1p, DSCP and MPLS EXP. In addition, this dissertation presents methods, techniques and configurations of switches and routers that allow for the expansion of QoS from the network layer at a lower layer, thereby providing a consistent QoS level both at Layer 3 and Layer 2. Finally, the automated delivery/provision of these services in a real production network, GRNET, is presented. More specifically, the modeling of L2 QoS-enabled switches is described along with the automated configuration production for providing integrated QoS and issues related to the discovery, mapping and monitoring of QoS in switches using the SNMP protocol. The effectiveness of Layer 2 QoS mechanisms was tested and reinforced with experiments, which were conducted small scale at first in the lab and in the department of the University and then moved on to large scale at the production network of GRNET. The experiments showed that regardless of the expansion of a network towards Layer 2 devices, it is feasible to provide a unified QoS framework. All the above resulted in the provisioning of end-to-end QoS services at GRNET’s network.

Made available in DSpace on 2013-08-07T18:53:03Z (GMT). No. of bitstreams: 1 000395124-Texto+Completo-0.pdf: 1485381 bytes, checksum: 9936ed7d7bb8dd338419e42e6aea0c89 (MD5) Previous issue date: 2007 / The constant increase of density in today´s programmable logic devices (FPGA’s), together with the lowering of prices of these integrated circuits, has been making possible the implementation of complex systems which, some time ago, would require dedicated integrated circuits. In designs where an FPGA is already in use, it is even easier to justify the integration of new functionalities to the programmable logic project, as the costs involving the software and hardware development tools have already been used. This work implements an Ethernet bridge using a system composed by softprocessor, where the functions related to the packet classification and forwarding are executed in software, what makes the system far more versatile and friendly to implementation changes in the future, as well as easy maintenance. Besides the softprocessor, implemented in VHDL there are the media access controller (MAC) and an HDLC controller, which is used as the connection point between the local and remote bridges. The prototyping of the system, to evaluate the performance, has been done using the software tools and development boards from Xilinx, since they were easily accessible and offer the MicroBlaze softprocessor IP core, a 32 bit RICS processor with harvard architecture. The performance analysis of the system, done with use of software tools like Iperf and hardware tools like SmartBits, has shown that the bridge was fast enough to handle small packets at a rate over 1Mbps. For larger packets, the performance was close to the 2Mbps, which represent the maximum typical rate where this bridge will be inserted in the real applications. Due to its extremely versatile nature, having been implemented using programmable logic and software functions, the system can handle the inclusion of new features in future activities, such as packet filtering, virtual LAN’s and the Spanning Tree Protocol. Besides these new software functionalities, new hardware modules can also be inserted, be it either to implement new features, such as the increase in the number of WAN interfaces, or to simply optimize existing logic blocks. / O constante aumento na densidade dos dispositivos de lógica programável (FPGA’s), aliado à diminuição dos preços destes circuito integrados, tem viabilizado a implementação de sistemas complexos, que antes necessariamente implicavam no uso de circuitos integrados dedicados. Em projetos onde um FPGA já é utilizado, justifica-se ainda mais facilmente a integração de novas funcionalidades ao projeto de lógica programável, uma vez que os custos envolvendo as ferramentas de desenvolvimento, tanto de hardware quanto de software, já foram contabilizados. Este trabalho implementa uma bridge ethernet através de um sistema composto por um softprocessor, onde as funções relativas à classificação e encaminhamento dos pacotes são realizadas em software, o que torna o sistema mais acessível à mudanças na implementação e de fácil manutenção. Além do softprocessor, implementados em VHDL ainda temos um controlador de acesso ao meio físico ethernet (MAC) e um controlador HDLC o qual é utilizado como ponto de ligação entre as bridge local e a bridge remota. A prototipagem do sistema, para avaliação e análise de desempenho, é feita com o uso das ferramentas de software e placas de desenvolvimento de hardware da Xilinx, por serem de fácil acesso e que oferecem o núcleo de softprocessor MicroBlaze, um microprocessador RISC de 32 bits com arquitetura harvard. A análise de desempenho do sistema, realizada com o auxílio de ferramentas de software (Iperf) e hardware (SmartBits), mostrou que a bridge consegue atingir taxas acima de 1Mbps com pacotes pequenos (64 bytes), típicos das aplicações VoIP. Para pacotes maiores, o desempenho se aproximou dos 2 Mbps, que representam a taxa típica máxima onde este dispositivo será usado na prática. Devido à sua natureza extremamente maleável, em vista da utilização de lógica programável e de funções de software, o sistema permite a inclusão de novas facilidades em atividades futuras, tais como a filtragem de pacotes, redes locais virtuais (VLAN’s) e o protocolo Spanning Tree. Além de novas funcionalidades de software, novos módulos do hardware sintetizável também podem ser incorporados, sejam para desempenhar novas funções, tais como o aumento das interfaces WAN, como para otimizar módulos já existentes.

The computer engineering group at Linköping University has parts of their research dedicated to networks-on-chip and components used in network components and terminals. This research has among others resulted in the SoCBUS NOC and a flow based network protocol processor. The main objective of this project was to integrate these components into an IP router with two or more Gigabit Ethernet interfaces. A working system has been designed and found working. It consists of three main components, the input module, the output module and a packet buffer. Due to the time constraint and the size of the project the packet buffer could not be designed to be as efficient as possible, thus reducing the overall performance. The SoCBUS also has negative impact on performance, although this could probably be reduced with a revised system design. If such a project is carried out it could use the input and output modules from this project, which connect to SoCBUS and can easily be integrated with other packet buffers and system designs.

The computer engineering department at Linköping University has a research project which investigates the use of an on-chip network in a router. There has been an implementation of it in a FPGA and for this router there is a need for buffer memory. This thesis extends the router design with a DDR memory controller which uses the features provided by the Virtex-II FPGA family. The thesis shows that by carefully scheduling the DDR SDRAM memory high volume transfers are possible and the memory can be used quite effciently despite its rather complex interface. The DDR memory controller developed is part of a packet buffer module which is integrated and tested with a previous, slightly modifed, FPGA based router design. The performance of this router is investigated using real network interfaces and due to the poor network performance of desktop computers special hardware is developed for this purpose.

Med en växande produktionsindustri i Asien så blir det allt svårare för företag i Europa och Sverige att konkurrera med den effektiva och framförallt billiga arbetskraft som erbjuds i öst. För att kunna konkurrera på ett effektivt sätt så har industrirobotindustrin växt kraftigt under de senaste åren. Detta är en rapport på hur ett koncept har påbörjats för att implementera ett Ethernet baserat kommunikationssystem kallat EtherCAT i ett robotsystem från Motoman. En testutrustning har byggts och simulerat en kommunikation med en PLC. Ett första HMI gränssnitt har skrivits som översätter informationen från PLCn för att göra informationen lättförståelig för människor. Det har förberetts ett robotprogram till en robot från Motoman. Rapporten innehåller också en faktadel för hur EtherCAT fungerar och en jämförelse med andra systembussar. / With a fast growing production industry in Asia it’s getting harder and harder for Swedish companies to compete with the low production cost that the east offers. To be more competitive robot solutions are used more and more. This is a report of a first concept to implement a new Ethernet based communication called EtherCAT, in one of Motoman robot controllers. Test equipment has been constructed and simulated a communication with the PLC. A first HMI interface has been written to show the information from the PLC in a way that is understandable for humans. For one of Motoman’s robots a program has been prepared.

Here at ISY research is performed on network processors. In order to evaluate the processors there is a need to have full control of every aspect of the transmission. This is not the case if you use a proprietary technology. Therefore the need for a well documented gigabit Ethernet network interface has emerged. The purpose of this thesis work has been to design and implement an open source gigabit Ethernet controller in a FPGA together with a device driver for the Linux operating system Implementation has been done in Verilog for the hardware part and the software was developed in C. We have implemented a fully functional gigabit Ethernet interface onto a Xilinx Virtex II-1500 FPGA together with a Linux device driver. The design uses approximately 7200 LUTs and 48 block RAMs including the opencores PCI bridge.