Impedance-based methods are used to locate faults on distribution systems because of their simplicity and ease of implementation. These methods require fault voltage and current data along with the positive- and zero-sequence line impedance values (in ohm per unit length) to estimate the reactance or distance to fault location. Inaccuracies in line impedance values, which arise from circuit model errors, have an adverse impact on fault location estimates of the impedance-based methods. Measurement errors in current and voltage transformers can also lead to inaccuracy in estimation. Further, all methods use simplistic models to represent the system load. The load in a practical distribution system does not conform to the oversimplified models leading to errors in estimation of fault location. This thesis presents sensitivity analysis of four impedance-based methods. It focuses on the Takagi, positive-sequence reactance, loop reactance and balanced-load methods. Amongst these four methods, the first three are commonly used for fault location. The fourth method was developed as a part of this work. The objective of sensitivity analysis is to study and quantify the effect of circuit model, measurement and load model errors, on the fault location estimates of the four methods. The results of this analysis are used to establish upper and lower bounds on the estimation errors for each method. The analysis begins with creation of a baseline case using a modified version of the IEEE 34 Node Test Feeder. All the methods estimate the reactance to fault location as a part of this analysis. The baseline case uses accurate line impedances and measurement values in the four methods. The fault location estimates for this case serve as a means of comparison for all subsequent analyzes. Secondly, various circuit model errors are introduced while computing the line impedance values. These errors include inaccurate modeling of four parameters viz. phase conductor distances, conductor sizes, phase to neutral conductor distances and earth resistivity. The erroneous line impedance values, which arise from these circuit model errors, are used in the four methods. The resultant location estimates are compared with those for the baseline case. It is observed that modeling errors in earth resistivity can cause estimation errors of 2% to 5% in the Takagi and positive-sequence reactance methods. These errors can be positive or negative depending upon whether the modeled earth resistivity value is more than or less than the accurate value. The effect of inaccurate modeling of the other three parameters is marginal. Additionally, the Takagi and positive-sequence reactance methods assume line impedances to be uniform while estimating fault location. Although this assumption is a type of circuit model error, it does not lead to significant errors in estimation. The loop reactance and balanced-load methods are insensitive to circuit model errors as they do not use line impedance values while estimating reactance to fault location. The next part is analysis of effect of measurement errors on fault location estimates. Ratio and phase angle errors are deliberately introduced in the current and voltage transformers and the erroneous measurements are used to conduct fault location. This causes 5% to 6% errors in estimation for the Takagi and positive-sequence reactance methods. These estimation errors can be positive or negative depending upon the magnitude of the CT and VT ratio errors and the sign of the phase angle errors. For the loop reactance method, erroneous measurements introduce 8% to 30% errors in fault location. This indicates that the loop reactance method is highly sensitive to measurement errors. The balanced-load method is moderately sensitive and experiences 6% to 7% errors in fault location estimates. Lastly, the effect of load current on fault location estimates is analyzed. When the Takagi and positive-sequence reactance methods are used on a heavily loaded system, they estimate fault location with an error of 5% to 8%. The loop reactance method is severely affected by the level of load current in the system. This method can estimate fault location with nearly 100% accuracy, on a lightly loaded system. However, the estimation errors for this method increase significantly and are in the range of 15% to 30%, as load current in the system increases. In case of the balanced-load method, unbalanced, heavy loads can cause estimation errors of 7% to 25%. The combined effect of all the error sources is taken into account by creating a confidence interval for each method. For the Takagi and positive-sequence reactance methods, the actual fault location can be expected to lie within ±10% of the estimated value. The fault location estimation error for the loop reactance and balanced-load methods is always positive. The actual reactance-to-fault is within -30% of the value estimated by these methods. / text

The Weepah Hills Area (Nevada) exposes exhumed metamorphic and plutonic rocks and upper-plate (supradetachment) volcano-sedimentary rocks that have experienced a complex, multi-stage deformational and depositional history. The Weepah Hills metamorphic core complex (WHMCC) is located in a region of the western Cordillera that was affected by both Miocene Basin-and-Range style E-W extension and Mio-Pliocene Walker Lane transcurrent shearing. Mio-Pliocene transcurrent deformation is transferred across a ~175 km releasing bend, known as the Mina Deflection, that kinematically links dextral strike-slip faults of the Death Valley-Fish Lake Valley with the central Walker Lane Belt. Progressive Mio-Pliocene transtension is characterized by core complex detachment faulting and younger high-angle normal faults. Timing of detachment faulting is constrained by both (U-Th)/He thermochronometry of footwall rocks and detailed chronostratigraphy of upper-plate strata to between 9-6 Ma. This age is supported by deformation recorded in the upper-plate strata that is attributed to progressive folding of the detachment associated with corrugation development. Earlier Miocene Basin-and-Range style extension is characterized by N-S trending high-angle normal faults and half-grabens that are strongly overprinted by Mio-Pliocene structures. (U-Th)/He zircon cooling ages from the detachment footwall range from ~12-20 Ma and are attributed to exhumation and unroofing related to E-W Basin-and-Range extension. New detailed sedimentological and geochronologic data show that, in contrast to previous research, the WHMCC upper-plate strata do not form a single supradetachment package, but rather three temporally distinct Miocene stratigraphic packages bounded by angular unconformities. The stratigraphic, structural, and exhumational record preserved in the WHMCC elucidates the timing of deformation and sedimentary basin evolution related to both Basin-and-Range E-W extension and Walker Lane related NW-directed transtension. / text

As confirmed by a recent survey conducted among developers of the Apache, Eclipse, and Mozilla projects, two extremely challenging tasks during maintenance are reproducing and debugging field failures--failures that occur on user machines after release. In my PhD study, I have developed several techniques to address and mitigate the problems of reproducing and debugging field failures. In this defense, I will present an overview of my work and describe in detail four different techniques: BugRedux, F3, Clause Weighting (CW), and On-demand Formula Computation (OFC). BugRedux is a general technique for reproducing field failures that collects dynamic data about failing executions in the field and uses this data to synthesize executions that mimic the observed field failures. F3 leverages the executions generated by BugRedux to perform automated debugging using a set of suitably optimized fault-localization techniques. OFC and CW improves the overall effectiveness and efficiency of state-of-the-art formula-based debugging. In addition to the presentation of these techniques, I will also present an empirical evaluation of the techniques on a set of real-world programs and field failures. The results of the evaluation are promising in that, for all the failures considered, my approach was able to (1) synthesize failing executions that mimicked the observed field failures, (2) synthesize passing executions similar to the failing ones, and (3) use the synthesized executions successfully to perform fault localization with accurate results.

Good failure analysis is the ability to determine the site of a circuit defect quickly and accurately. We propose a method for defect site prediction that is based on a site's probability of excitation, making no assumptions about the type of defect being analyzed. We do this by analyzing fault signatures and comparing them to the defect signature. We use this information to construct an ordered list of sites that are likely to be the site of the defect.

The semiconductor technology development empowers fabrication of extremelycomplex integrated circuits (ICs) that may contain billions of transistors. Suchhigh integration density enables designing an entire system onto a single chip,commonly referred to as a System-on-Chip (SoC). In order to boost performance,it is increasingly common to design SoCs that contain a number of processors, socalled multi-processor system-on-chips (MPSoCs).While on one hand, recent semiconductor technologies enable fabrication ofdevices such as MPSoCs which provide high performance, on the other hand thereis a drawback that these devices are becoming increasingly susceptible to faults.These faults may occur due to escapes from manufacturing test, aging effects orenvironmental impacts. When present in a system, faults may disrupt functionalityand can cause incorrect system operation. Therefore, it is very importantwhen designing systems to consider methods to tolerate potential faults. To copewith faults, there is a need of fault handling which implies automatic detection,identification and recovery from faults which may occur during the system’s operation.This work is about the design and implementation of a fault handling methodsfor an MPSoC. A fault aware Resource Manager (RM) is designed and implementedto obtain correct system operation and maximize the system’s throughputin the presence of faults. The RM has the responsibility of scheduling jobs to availableresources, collecting fault states from resources in the system and performingfault handling tasks, based on fault states. The RM is also employed in multipleexperiments in order to study its behavior in different situations.

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