This work presents a new approach for detecting and isolating faults in nonlinear processes using independent neural network models. In this approach, an independent neural network is used to model the proton exchange membrane fuel cell nonlinear systems using a multi-input multi-output structure. This research proposed the use of radial basis function network and multilayer perceptron network to perform fault detection. After training, the neural network models can give accurate prediction of the system outputs, based on the system inputs. Using the residual generation concept developed in the model-based diagnosis, the difference between the actual and estimated outputs are used as residuals to detect faults. When the magnitude of these residuals exceed a predefined threshold, it is likely that the system is faulty. In order to isolate faults in the system, a second neural network is used to examine features in the residual. A specific feature would correspond to a specific fault. Based on features extracted and classification principles, the second neural network can isolate faults reliably and correctly. The developed method is applied to a benchmark simulation model of the proton exchange membrane fuel cell stacks developed at Michigan University. One component fault, one actuator fault and three sensor faults were simulated on the benchmark model. The simulation results show that the developed approach is able to detect and isolate the faults to a fault size of ±10% of nominal values. These results are promising and indicate the potential of the method to be applied to the real world of fuel cell stacks for dynamic monitoring and reliable operations.

The focus of the work in this thesis is concerned with the investigation and development of indirect measurement techniques. The methodology adopted is a combination of practical experimental, analytical deductive reasoning and simulation studies. This has led to proposals for a number of indirect tyre pressure monitoring systems, which are able to detect pressure loss under specific circumstances. The outcome overall is a proposal for a new supervisory system comprising of a modular framework, allowing various algorithms and techniques to be implemented in a complementary manner as they emerge and data sources become available. A number of contributions to the field have been made, which to the knowledge of the author, provide potential for further algorithm development and are imminently applicable given the above. The methods include a tyre pressure diagnosis via a wheel angular velocity comparator, the development of a model-based tyre pressure diagnosis via application of an unknown input observer and a parameter estimation scheme, a model-based tyre pressure diagnosis approach via an enhanced Kalman filter configured to estimate states including the input, a model-based tyre pressure diagnosis via cautious least squares, an investigation and critique of the effects of the choice of sampling interval on discrete-time models and estimation thereof. It is considered, that the extensive literature review provides a valuable historic insight into the tyre fault detection problem. It is clear, from the development and testing of the algorithms (and also the literature), that no single indirect pressure detection method is able to reliably detect changes in all driving scenarios which the regulations typically stipulate (depending on jurisdiction). In the absence of any information about the road input, the majority of the detection work must be shouldered by the wheel angular velocity comparator algorithm. As image recognition and sensor technology develops, it becomes possible to make estimates about the road surface and this removes some of the uncertainty on the input of the model-based parameter estimation approaches. Further work is detailed which goes some way towards realising the next steps in a development cycle suitable for a vehicle manufacturer to take through to the implementation stage.

Wrinkle ridges are among the most common tectonic structures on the terrestrial planets and provide important records of the history of planetary strain and geodynamics. The observed broad arches and superposed narrow wrinkles are thought to be the surface manifestation of blind thrust faults, which terminate in near-surface volcanic sequences and cause folding and layer-parallel shear. However, the subsurface tectonic architecture associated with the ridges remains a matter of debate. Here we present direct observations of a wrinkle ridge thrust fault where it has been exposed by erosion in the southern wall of Melas Chasma on Mars. The thrust fault has been made resistant to erosion, likely due to volcanic intrusion, such that later erosional widening of the trough exposed the fault plane as a 70km long ridge extending into the chasma. A plane fit to this ridge crest reveals a thrust fault with a dip of 13 degrees (+8 degrees, -7 degrees) between 1 and 3.5km depth below the plateau surface, with no evidence for listric character in this depth range. This dip is significantly lower than the commonly assumed value of 30 degrees, which, if representative of other wrinkle ridges, indicates that global contraction on Mars may have been previously underestimated.

[EN] Relevance of electronics towards safety of common devices has only been growing, as an ever growing stake of the functionality is assigned to them. But of course, this comes along the constant need for higher performances to fulfill such functionality requirements, while keeping power and budget low. In this scenario, industry is struggling to provide a technology which meets all the performance, power and price specifications, at the cost of an increased vulnerability to several types of known faults or the appearance of new ones. To provide a solution for the new and growing faults in the systems, designers have been using traditional techniques from safety-critical applications, which offer in general suboptimal results. In fact, modern embedded architectures offer the possibility of optimizing the dependability properties by enabling the interaction of hardware, firmware and software levels in the process. However, that point is not yet successfully achieved. Advances in every level towards that direction are much needed if flexible, robust, resilient and cost effective fault tolerance is desired. The work presented here focuses on the hardware level, with the background consideration of a potential integration into a holistic approach. The efforts in this thesis have focused several issues: (i) to introduce additional fault models as required for adequate representativity of physical effects blooming in modern manufacturing technologies, (ii) to provide tools and methods to efficiently inject both the proposed models and classical ones, (iii) to analyze the optimum method for assessing the robustness of the systems by using extensive fault injection and later correlation with higher level layers in an effort to cut development time and cost, (iv) to provide new detection methodologies to cope with challenges modeled by proposed fault models, (v) to propose mitigation strategies focused towards tackling such new threat scenarios and (vi) to devise an automated methodology for the deployment of many fault tolerance mechanisms in a systematic robust way. The outcomes of the thesis constitute a suite of tools and methods to help the designer of critical systems in his task to develop robust, validated, and on-time designs tailored to his application. / [ES] La relevancia que la electrónica adquiere en la seguridad de los productos ha crecido inexorablemente, puesto que cada vez ésta copa una mayor influencia en la funcionalidad de los mismos. Pero, por supuesto, este hecho viene acompañado de una necesidad constante de mayores prestaciones para cumplir con los requerimientos funcionales, al tiempo que se mantienen los costes y el consumo en unos niveles reducidos. En este escenario, la industria está realizando esfuerzos para proveer una tecnología que cumpla con todas las especificaciones de potencia, consumo y precio, a costa de un incremento en la vulnerabilidad a múltiples tipos de fallos conocidos o la introducción de nuevos. Para ofrecer una solución a los fallos nuevos y crecientes en los sistemas, los diseñadores han recurrido a técnicas tradicionalmente asociadas a sistemas críticos para la seguridad, que ofrecen en general resultados sub-óptimos. De hecho, las arquitecturas empotradas modernas ofrecen la posibilidad de optimizar las propiedades de confiabilidad al habilitar la interacción de los niveles de hardware, firmware y software en el proceso. No obstante, ese punto no está resulto todavía. Se necesitan avances en todos los niveles en la mencionada dirección para poder alcanzar los objetivos de una tolerancia a fallos flexible, robusta, resiliente y a bajo coste. El trabajo presentado aquí se centra en el nivel de hardware, con la consideración de fondo de una potencial integración en una estrategia holística. Los esfuerzos de esta tesis se han centrado en los siguientes aspectos: (i) la introducción de modelos de fallo adicionales requeridos para la representación adecuada de efectos físicos surgentes en las tecnologías de manufactura actuales, (ii) la provisión de herramientas y métodos para la inyección eficiente de los modelos propuestos y de los clásicos, (iii) el análisis del método óptimo para estudiar la robustez de sistemas mediante el uso de inyección de fallos extensiva, y la posterior correlación con capas de más alto nivel en un esfuerzo por recortar el tiempo y coste de desarrollo, (iv) la provisión de nuevos métodos de detección para cubrir los retos planteados por los modelos de fallo propuestos, (v) la propuesta de estrategias de mitigación enfocadas hacia el tratamiento de dichos escenarios de amenaza y (vi) la introducción de una metodología automatizada de despliegue de diversos mecanismos de tolerancia a fallos de forma robusta y sistemática. Los resultados de la presente tesis constituyen un conjunto de herramientas y métodos para ayudar al diseñador de sistemas críticos en su tarea de desarrollo de diseños robustos, validados y en tiempo adaptados a su aplicación. / [CAT] La rellevància que l'electrònica adquireix en la seguretat dels productes ha crescut inexorablement, puix cada volta més aquesta abasta una major influència en la funcionalitat dels mateixos. Però, per descomptat, aquest fet ve acompanyat d'un constant necessitat de majors prestacions per acomplir els requeriments funcionals, mentre es mantenen els costos i consums en uns nivells reduïts. Donat aquest escenari, la indústria està fent esforços per proveir una tecnologia que complisca amb totes les especificacions de potència, consum i preu, tot a costa d'un increment en la vulnerabilitat a diversos tipus de fallades conegudes, i a la introducció de nous tipus. Per oferir una solució a les noves i creixents fallades als sistemes, els dissenyadors han recorregut a tècniques tradicionalment associades a sistemes crítics per a la seguretat, que en general oferixen resultats sub-òptims. De fet, les arquitectures empotrades modernes oferixen la possibilitat d'optimitzar les propietats de confiabilitat en habilitar la interacció dels nivells de hardware, firmware i software en el procés. Tot i això eixe punt no està resolt encara. Es necessiten avanços a tots els nivells en l'esmentada direcció per poder assolir els objectius d'una tolerància a fallades flexible, robusta, resilient i a baix cost. El treball ací presentat se centra en el nivell de hardware, amb la consideració de fons d'una potencial integració en una estratègia holística. Els esforços d'esta tesi s'han centrat en els següents aspectes: (i) la introducció de models de fallada addicionals requerits per a la representació adequada d'efectes físics que apareixen en les tecnologies de fabricació actuals, (ii) la provisió de ferramentes i mètodes per a la injecció eficient del models proposats i dels clàssics, (iii) l'anàlisi del mètode òptim per estudiar la robustesa de sistemes mitjançant l'ús d'injecció de fallades extensiva, i la posterior correlació amb capes de més alt nivell en un esforç per retallar el temps i cost de desenvolupament, (iv) la provisió de nous mètodes de detecció per cobrir els reptes plantejats pels models de fallades proposats, (v) la proposta d'estratègies de mitigació enfocades cap al tractament dels esmentats escenaris d'amenaça i (vi) la introducció d'una metodologia automatitzada de desplegament de diversos mecanismes de tolerància a fallades de forma robusta i sistemàtica. Els resultats de la present tesi constitueixen un conjunt de ferramentes i mètodes per ajudar el dissenyador de sistemes crítics en la seua tasca de desenvolupament de dissenys robustos, validats i a temps adaptats a la seua aplicació. / Espinosa García, J. (2016). New Fault Detection, Mitigation and Injection Strategies for Current and Forthcoming Challenges of HW Embedded Designs [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/73146 / TESIS

The main topic of this licentiate thesis is fast faultdetection. The thesis summaries the work performed in theproject“Fast fault detection for distributionsystems”. In the first chapters of the thesis the term“fast”is used in a general manner. The term is laterdefined based upon considerations and conclusions made in thefirst chapters and then related to a specific time. To be able to understand and appreciate why fast faultdetection is necessary, power system faults and theirconsequences are briefly discussed. The consequences of a faultare dependent of a number of different factors, one of thefactors being the duration of the fault. The importance of the speed of the fault detection dependson the type of equipment used to clear the fault. A circuitbreaker which interrupt currents only when they pass through anatural zero crossing might be less dependent on the speed ofthe fault detection than a fault current limiter which limitsthe fault current before it has reached its first prospectivecurrent peak. In order to be able to detect a fault in a power system, thepower system must be observed, i.e., measurements of relevantquantities must be performed so that the fault detectionequipment can obtain information of the state of the system.The fault detection equipment and some general methods of faultdetection are briefly described. Some algorithms and their possible adaptation to fast faultdetection are described. A common principle of many algorithmsare that they assume that either a signal or the power systemobject can be described by a model. Sampled data values arethen fitted to the model so that an estimate of relevantparameters needed for fault detection is obtained. An algorithmwhich do not fit samples to a model but use instantaneouscurrent values for fault detection is also described andevaluated. Since the exact state of a power system never is known dueto variations in power production and load, a model of thepower system or of the signal can never be perfect, i.e., theestimated parameter can never be truly correct. Furthermore,errors from the data acquisition system contribute to the totalerror of the estimated parameter. Two case studies are used to study the performance of the(modified) algorithms. For those studies it has been shown thatthe algorithms can detect a fault within approximately 1msafter fault inception and that one of the algorithms candiscriminate between a fault and two types of common powersystem transients (capacitor and transformer energization). The second case study introduced a system with two sourceswhich required a directional algorithm to discriminate betweenfaults inside or outside the protection zone. It is concluded that under certain assumptions it ispossible to detect power system faults within approximately 1msand that it is possible to discriminate a power system faultfrom power system transient that regularly occurs within powersystems but which not are faults. / NR 20140805

Snehal Udar, for the Doctor of Philosophy degree in Electrical and Computer Engineering, presented on May 4, of 2011, at Southern Illinois University Carbondale. TITLE: BUILT-IN SCHEMES FOR TEST PATTERN GENERATION AND FAULT LOCATION MAJOR PROFESSOR: Dr. D. Kagaris In this dissertation, we studied the areas of test pattern generation and fault location for detecting and diagnosing the faults in today's complex chips. In the first problem, a novel reseeding based test pattern generation scheme is analyzed by proposing a hardware efficient technique that uses irreducible polynomial-primitive element pair to generate distinct subsequences of test patterns. It is shown that for the given characteristic polynomial the hardware cost remains the same irrespective of the number of seeds required to generate the test sequence of given length. This scheme is targeted at generating pseudo-random test patterns that detect easy-to-detect faults. A counter based reseeding scheme is further analyzed that embeds a given set of fully specified test patterns in minimum number of clock cycles. Second problem investigates the effectiveness of inserting observation points on the circuit lines that along with primary output lines distinguish a given set of faults. Three hardware based approaches are proposed that aim at inserting minimum observation points, and are compared with each other for different diagnostic resolutions.

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