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Popularly used impedance-based methods need voltage and current waveform as well as line impedance per unit length to estimate distance to fault location. For a non-homogenous system with different line configuration, these methods assume that the system is homogenous and use the line impedance of the most frequently occurring line configuration. Load present in the system before fault is an important parameter which affects fault location accuracy. Impedance-based methods like Takagi and positive-sequence method assume that the load is lumped beyond the fault point which may not be true for a typical distribution system. As a result, accuracy of the impedance-based methods in estimating distance to fault is affected. Another short-coming of impedance-based methods are that they are unable to identify the branch in which the fault may be located. To minimize these errors, this thesis proposes a short-circuit fault current profile approach to complement impedance-based algorithms. In the short-circuit fault current profile approach, circuit model of the distribution feeder is used to place faults at every bus and the corresponding short-circuit fault current is plotted against reactance or distance to fault. When a fault occurs in the distribution feeder, fault current recorded by relay is extrapolated on the current profile to get location estimates. Since the circuit model is directly used in building the current profile, this approach takes into account load and non-uniform line impedance. Using the estimates from short-circuit fault current profile approach and impedance-based methods, the path on which the fault is located is identified. Next to improve fault location estimates, a median value of the estimates is computed. The median is a more robust estimate since it is not affected by outliers. The strategy developed above is tested using modified IEEE 34 Node Test Feeder and validated against field data provided by utilities. For the IEEE 34 Node Test Feeder, it is observed that the median estimate computed from impedance-based methods and the short-circuit fault current profile approach is very close to the actual fault location. Error in estimation is within 0.58 miles. It was also observed that if a 0.6 mile radius is built around the median estimate, the fault will lie within that range. Now the IEEE 34 Node Test Feeder represents a typical distribution feeder and has also been modeled to represent the worst case scenario, i.e. load current is around 51% of the fault current for the farthest bus. Hence the 0.6 mile radius around the median estimate will hold true for most distribution feeders and will be used when computing the fault range for field case events. For the field events, it was seen that the actual faults indeed lie within the 0.6 mile radius built around the median estimate and the path of the fault location has also been accurately estimated. For certain events, voltage waveform was not useful for analysis. In such situations, short-circuit fault current profile alone could be used to estimate fault location. Error in estimation is within 0.1 miles, provided the circuit model closely represents the distribution feeder. / text

The thesis begins with an introduction to transformer theory. The partial core transformer is then introduced and compared with a full core design. A brief introduction to superconductors and high temperature superconductors is then presented. High temperature superconducting fault current limiters are then examined and the advantage of a high temperature superconducting partial core transformer and fault current limiter as a single unit is highlighted. The reverse design model is discussed followed by the model parameters that are used in designing the high temperature superconducting partial core transformer. Partial core transformers with copper windings and high temperature superconductor windings at the University of Canterbury were then tested and the measured results compared with the results calculated from the reverse design model, to validate the model. The high temperature superconducting partial core transformer failed during an endurance run and the investigation of the failure is then presented. The results of the failure investigation prompted an alternative winding insulation design. A model to calculate the time at which the high temperature superconducting winding of the partial core transformer would melt at different currents was then built. The time was calculated to be used in the operation of the quench detection mechanism and it could also be used in choosing a circuit breaker with a known operating time. The design of the high temperature superconducting partial core transformer and fault current limiter is then presented. Design configurations with different core length and winding length are examined. The idea behind choosing the final design for the high temperature superconducting partial core transformer and fault current limiter is then discussed. The final design of the high temperature superconducting partial core transformer and fault current limiter is then presented. A new 7.5 kVA, 230-248 V high temperature superconducting partial core transformer and fault current limiter was designed, built and tested. The windings are layer wound with first generation Bi2223 high temperature superconductor. A series of electrical tests were performed on the new device including open circuit, short circuit, resistive load, overload and fault ride through. These tests were performed to determine the operational characteristics of the new high temperature superconducting partial core transformer and fault current limiter. The measured results from the tests were compared with the calculated results. The fault ride through test results were then compared to a 15 kVA high temperature superconducting partial core transformer that was designed and built at the University of Canterbury. Since the resistive component of the silver matrix in Bi2223 high temperature superconductor plays a very little role in controlling the fault current, the current limited by the leakage reactance is compared between the two devices. The high temperature superconducting partial core transformer and fault current limiter was found to be 99.1% efficient at rated power with 5.7% regulation and fault current limiting ability of 500 % over the 15 kVA high temperature superconductor partial core transformer from University of Canterbury.

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Superconductivity Centennial Conference 2011- EUCAS–ISEC–ICMC (18-23 Sep 2011, The Hague, The Netherlands)

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